參數(shù)資料
型號: CYP15G0101DXA-BBC
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 41/78頁
文件大小: 1555K
代理商: CYP15G0101DXA-BBC
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 41 of 78
Transmitter LVTTL Switching Characteristics
Receiver LVTTL Switching Characteristics
Parameter
Description
Min.
20
6.66
2.2
2.2
0.7
0.7
1.5
1
20
6.66
47
1.5
1.5
Max
150
50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
%
ns
ns
f
TS
t
TXCLK
t
TXCLKH
t
TXCLKL
t
TXCLKR [19, 20, 21]
t
TXCLKF [19, 20, 21]
t
TXDS
t
TXDH
f
TOS
t
TXCLKO
t
TXCLKOD
t
TXOH
t
TXOL
TXCLKx Clock Cycle Frequency
TXCLKx Period
TXCLKx HIGH Time
TXCLKx LOW Time
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-Up Time to
TXCLKx
(TXCKSEL
LOW)
Transmit Data Hold Time from TXCLKx
(TXCKSEL
LOW)
TXCLKO Clock Cycle Frequency (=1x or 2x REFCLK Frequency)
TXCLKO Period
TXCLKO Duty Cycle
TXCLKO HIGH Time
TXCLKO LOW Time
5
5
150
50
53
Parameter
Description
Min.
Max.
Unit
f
RS
t
RXCLKP
t
RXCLKH
RXCLKx Clock Output Frequency
10
150
MHz
RXCLKx Period
6.66
100
ns
RXCLKx HIGH Time (RXRATE = LOW)
1.5
51
ns
RXCLKx HIGH Time (RXRATE = HIGH)
5
25
ns
t
RXCLKL
RXCLKx LOW Time (RXRATE = LOW)
1.5
51
ns
RXCLKx HIGH Time (RXRATE = HIGH)
5
25
ns
t
RXCLKD
RXCLKR [19]
t
RXCLKF [19]
t
RXDS[22]
t
RXDH[22]
RXCLKx Duty Cycle
47
53
%
RXCLKx Rise Time
0.5
1.2
ns
RXCLKx Fall Time
0.5
1.2
ns
Status and Data Set-up Time From RXCLKx
Status and Data Hold Time From RXCLKx
2.0
ns
1.0
ns
Notes:
19. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
20. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
21. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30%-70%.
22. The ratio of rise time to falling time must not vary by greater than 2:1.
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