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| 型號(hào)： | CYP15G0101DXA-BBC |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 21/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101DXA-BBC |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 21 of 78
Serial Output Drivers
The serial interface Output Drivers make use of high-perfor-
mance differential CML (Current Mode Logic) to provide a
source-matched driver for the transmission lines. These driv-
ers accept data from the Transmit Shifters. These outputs have
signal swings equivalent to that of standard PECL drivers, and
are capable of driving AC-coupled optical modules or AC-cou-
pled transmission lines.
When configured for local loopback (LPEN = HIGH), the output
drivers for all enabled ports are configured to drive a static
differential logic-1.
Each output can be enabled or disabled separately through the
BOE[7:0] inputs, as controlled by the OELE latch-enable sig-
nal. When OELE is HIGH, the signals present on the BOE[7:0]
inputs are passed through the Serial Output Enable latch to
control the serial output drivers. The BOE[7:0] input associat-
ed with a specific OUTxy
±
driver is listed in
Table 16
.
When OELE is HIGH and BOE[x] is HIGH, the associated se-
rial driver is enabled to drive any attached transmission line.
When OELE is HIGH and BOE[x] is LOW, the associated driv-
er is disabled and internally configured for minimum power dis-
sipation. If both outputs for a channel are in this disabled state,
the associated internal logic for that channel is also configured
for lowest power operation. When OELE returns LOW, the val-
ues present on the BOE[7:0] inputs are latched in the Output
Enable Latch, and remain there until OELE returns HIGH to
opened the latch again.
Note:
When a disabled transmit channel (i.e., both outputs
disabled) is re-enabled, the data on the serial outputs may
not meet all timing specifications for up to 10 ms.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the transmit shifter. It also
provides a character-rate clock used by the transmit paths.
The clock multiplier PLL can accept a REFCLK input between
10 MHz and 150 MHz, however, this clock range is limited by
the operating mode of the PSI transceiver block clock multiplier
(controlled by TXRATE) and by the level on the SPDSEL input.
SPDSEL is a three-level select (ternary) input that selects one
of three operating ranges for the serial data outputs and inputs.
The operating serial signaling-rate and allowable range of
REFCLK frequencies are listed in
Table 17
.
The REFCLK
±
input is a non-standard input. It is implemented
as a differential input with each input internally biased to
V
/2. If the REFCLK+ input is connected to a TTL, LVTTL, or
LVCMOS clock source, the input signal is recognized when it
passes through the internally biased reference point.
When both the REFCLK+ and REFCLK
inputs are connect-
ed, the clock source must be a differential clock. This can be
either a differential LVPECL clock that is DC- or AC-coupled,
or a differential LVTTL or LVCMOS clock.
By connecting the REFCLK
input to an external voltage
source or resistive voltage divider, it is possible to adjust the
reference point of the REFCLK+ input for alternate logic levels.
When doing so it is necessary to ensure that the 0V-differential
crossing point remain within the parametric range supported
by the input.
Frequency Agile PSI Receive Data Path
Serial Line Receivers
Two differential line receivers, INx1
±
and INx2
±
, are available
on each channel for accepting serial data streams. The active
line receiver on a channel is selected using the associated
INSELx input. The serial line receiver inputs are all differential,
and can accommodate wire interconnect and filtering losses
or transmission line attenuation greater than 16 dB
(V
DIF
> 100 mV, or 200 mV peak-to-peak differential) or can be
DC- or AC-coupled to +3.3V powered fiber-optic interface
modules (any ECL/PECL logic family, not limited to 100K
PECL) or AC-coupled to +5V powered optical modules. The
common-mode tolerance of these line receivers accommo-
dates a wide range of signal termination voltages. Each receiv-
er provides internal DC-restoration, to the center of the receiv-
er
’
s common mode range, for AC-coupled signals.
The local loopback input (LPEN) allows the serial transmit data
outputs to be routed internally back to the Clock and Data Re-
covery circuit associated with each channel. When configured
for local loopback, all transmit serial driver outputs are forced
to output a differential logic-1. This prevents local diagnostic
patterns from being broadcast to attached remote receivers.
Signal Detect / Link Fault
Each selected Line Receiver (i.e., that routed to the Clock and
Data Recovery PLL) is simultaneously monitored for
analog amplitude
Table 16. Output Enable, BIST, and Receive Channel
Enable Signal Map
BOE
Input
BOE[7]
BOE[6]
BOE[5]
BOE[4]
BOE[3]
BOE[2]
BOE[1]
BOE[0]
Output
Controlled
(OELE)
OUTD2
±
OUTD1
±
OUTC2
±
OUTC1
±
OUTB2
±
OUTB1
±
OUTA2
±
OUTA1
±
BIST
Channel
Enable
(BISTLE)
Transmit D
Receive D
Transmit C
Receive C
Transmit B
Receive B
Transmit A
Receive A
Receive PLL
Channel
Enable
(RXLE)
X
Receive D
X
Receive C
X
Receive B
X
Receive A
Table 17. Operating Speed Settings
SPDSEL
LOW
TXRATE
1
0
1
0
1
0
REFCLK
Frequency
(MHz)
10
–
20
20
–
40
20
–
40
40
–
80
40
–
75
80
–
150
Signaling
Rate
(MBaud)
200
–
400
MID (Open)
400
–
800
HIGH
800
–
1500
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0403DXB | Physical Layer Devices |
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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