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參數(shù)資料
| 型號： | CYP15G0101 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single-channel HOTLink Transceiver |
| 中文描述： | 單通道的HOTLink收發(fā)器 |
| 文件頁數(shù)： | 6/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 6 of 78
Logic Block Cluster (LBC)
The PSI architecture consists of several logic block clusters,
each of which have 8 Logic Blocks (LB) and 2 cluster memory
blocks connected via a Programmable Interconnect Matrix
(PIM) as shown in
Figure 4
. Each cluster memory block con-
sists of 8-Kbit single-port RAM, which is configurable as syn-
chronous or asynchronous. The cluster memory blocks can be
cascaded with other cluster memory blocks within the same
LBC as well as other LBCs to implement larger memory func-
tions. If a cluster memory block is not specifically utilized by
the designer, Cypress
’
s
Warp
software can automatically use
it to implement large blocks of logic.
All LBCs interface with each other via horizontal and vertical
routing channels.
Figure 2. Block Diagram of a Standard Datapath Cell
D
Q
RES
E
G
O
G
Signal
From
Output PIM
To Routing
Channel
TE Mux
Register Receive
Mux
Register Enable
Mux
Transmit
Mux
Clock Mux
Clock
Polarity
Mux
Register Reset
Mux
Receive
Mux
D
Q
RES
C
Registered TE
Mux
C
C
C
3
C
3
C
2
3
C
C
C
Figure 3. PSI Routing Interface
LB
Cluster
PIM
Cluster
Memory
Block
LB
LB
LB
LB
Cluster
Memory
Block
LB
LB
LB
Channel
Memory
Block
I/O Block
I
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
72
72
64
64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
| CYPOSIC2GVC-K | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYS25G0101DX | Physical Layer Devices |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBC | 制造商:Cypress Semiconductor 功能描述:PHY 1-CH 100-Pin TBGA |
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
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