參數(shù)資料
型號: CYP15G0101
廠商: Cypress Semiconductor Corp.
英文描述: Single-channel HOTLink Transceiver
中文描述: 單通道的HOTLink收發(fā)器
文件頁數(shù): 44/78頁
文件大?。?/td> 1555K
代理商: CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 44 of 78
Transmitter Switching Waveforms
Note:
29. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW),
data is captured using both the rising and falling edges of REFCLK.
30. The TXCLKO output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLK.
31. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
TXCLKx
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
t
TXDH
t
TXDS
t
TXCLK
t
TXCLKH
t
TXCLKL
Transmit Interface
Write Timing
TXCKSEL
LOW
REFCLK
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = LOW
t
REFCLK
t
REFH
t
REFL
t
TREFDS
t
TREFDH
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
t
TREFDH
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
t
REFCLK
t
REFL
t
REFH
Note 29
TXDx[7:0],
TXCTx[1:0]
t
TREFDS
t
TREFDS
TXCLKO
(internal)
t
TXCLKO
t
TXOH
t
TXOL
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
t
REFCLK
t
REFL
t
REFH
Note 30
Note 31
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