參數(shù)資料
型號(hào)： CYP15G0101
廠商： Cypress Semiconductor Corp.
英文描述： Single-channel HOTLink Transceiver
中文描述： 單通道的HOTLink收發(fā)器
文件頁(yè)數(shù)： 31/78頁(yè)
文件大小： 1555K
代理商： CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 31 of 78
nal EEPROM. Configuration, on the other hand, is defined as
the loading of a user
’
s design into the volatile CPLD block.
Configuration can begin in two ways. It can be initiated by tog-
gling the
Reconfig
pin from LOW to HIGH, or by issuing the
appropriate IEEE std 1149.1 JTAG instruction to the PSI de-
vice via the JTAG interface. There are two IEEE std 1149.1
JTAG instructions that initiate configuration of the PSI. The
Self
Config
instruction causes the PSI to (re)configure with data
store in the internal EEPROM. The
Load Config
instruction
causes the PSI to (re)configure with data provided by other
sources such as a PC, automatic test equipment (ATE), or an
embedded microcontroller/processor via the JTAG port.
There are multiple configuration options available for issuing
the IEEE std 1149.1 JTAG instructions to the PSI. The first
method is to use a PC with the C3 ISR programming cable and
software. With this method, the ISR pins of the PSI devices in
the system are routed to a connector at the edge of the printed
circuit board. The C3 ISR programming cable is then connect-
ed between the PC and this connector. A simple configuration
file instructs the ISR software of the programming operations
to be performed on the PSI devices in the system. The ISR
software then automatically completes all of the necessary
data manipulations required to accomplish configuration,
reading, verifying, and other ISR functions. For more informa-
tion on the Cypress ISR interface, see the Programming/ISR
application notes at http://www.cypress.com/pld/pldapp-
notes.html.
For systems with embedded controllers/processors, a control-
ler/processor may be used to configure the PSI. The PSI ISR
software assists in this method by converting the device HEX
file into the ISR serial stream that contains the ISR instruction
information and the addresses and data of locations to be con-
figured. The controller/processor then simply directs this ISR
stream to the chain of PSI devices to complete the desired
reconfiguration or diagnostic operations. Contact your local
sales office for information on availability of this option.
Programming
The on-chip EEPROM device of the CPLD block is pro-
grammed by issuing the appropriate IEEE std 1149.1 JTAG
instruction. This can be done automatically using ISR/STAPL
software. The configuration bits are sent from a PC through the
JTAG port into the PSI via the C3 ISR programming cable. The
data is then passed to the internal EEPROM through the Non-
Volatile (NV) port of the CPLD block. For more information on
how to program the PSI through ISR/STAPL, please refer to
the ISR/STAPL User Guide.
Third-Party Programmers
Cypress support is available on a wide variety of third-party
programmers. All major programmers (including BP Micro,
System General, Hi-Lo) support the PSI family.
Development Software Support
Warp
Warp
is a state-of-the-art design environment for designing
with Cypress programmable logic.
Warp
utilizes a subset of
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware De-
scription Language (HDL) for design entry.
Warp
accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Delta39K device. For simulation,
Warp
provides a graphical
waveform simulator as well as VHDL and Verilog Timing Mod-
els.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process.
Third-Party Software
Cypress products are supported in a number of third-party de-
sign entry and simulation tools. Refer to the third-party soft-
ware data sheet or contact your local sales office for a list of
currently supported third party vendors.
Figure 15. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCLK
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