參數(shù)資料
型號(hào)： CYP15G0101
廠商： Cypress Semiconductor Corp.
英文描述： Single-channel HOTLink Transceiver
中文描述： 單通道的HOTLink收發(fā)器
文件頁數(shù)： 11/78頁
文件大?。?/td> 1555K
代理商： CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 11 of 78
Each PSI device has several types of user-programmable I/O
banks.
Table 3
indicates the availability of each type of pro-
grammable bank by device. Supported I/O standards for each
bank are addressed by the appropriate V
REF
and
V
CCIO
volt-
ages. All the V
REF
and V
CCIO
pins in an I/O bank must be
connected to the same V
and V
voltage respectively.
This requirement restricts the number of I/O standards sup-
ported by an I/O bank at any given time. It also dictates the I/O
standard used for the GCTL[3:0] pins.
The architecture defining each programmable I/O bank con-
sists of several I/O cells, where each I/O cell contains an in-
put/output register, an output enable register, programmable
slew rate control, and programmable bus hold control logic.
Each I/O cell drives a pin output of the device; the cell also
supplies an input to the device that connects to a dedicated
track in the associated routing channel.
There are four dedicated inputs (GCTL[3:0]) that are used as
Global Control Signals available to every I/O cell. These global
control signals may be used as output enables, register resets
and register clock enables as shown in
Figure 9
.
Figure 8. PSI I/O Bank Block Diagram
PSI
I/O Bank
I/O Bank
I/O Bank
I/O Bank
I
I
X
&
S
Table 3. IO Standards
I/O
Standard
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
V
REF
(V)
Min.
N/A
V
CCIO
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
N/A
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
Termination
Voltage (V
TT
)
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.25
1.25
0.75
0.75
1.5
1.5
Max.
0.9
1.3
1.3
1.15
1.15
0.68
0.68
0.68
0.68
1.1
1.7
1.7
1.35
1.35
0.9
0.9
0.9
0.9
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