參數(shù)資料
型號(hào)： CYP15G0101
廠商： Cypress Semiconductor Corp.
英文描述： Single-channel HOTLink Transceiver
中文描述： 單通道的HOTLink收發(fā)器
文件頁(yè)數(shù)： 25/78頁(yè)
文件大?。?/td> 1555K
代理商： CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 25 of 78
Each Elasticity Buffer is a minimum of 10-characters deep, and
supports a 11-bit wide data path. It is capable of supporting a
decoded character and three status bits for each character
present in the buffer. The write clock for these buffers is always
the recovered clock for the associated read channel.
The read clock for the Elasticity Buffers may come from one of
three selectable sources. It may be a
character-rate REFCLK
↑
recovered clock from the same receive channel
recovered clock from an alternate receive channel
These Elasticity Buffers are also used to align the output data
streams when multiple channels are bonded together.
Receive Modes
The operating mode of the receive path is set through the
RXMODE[1:0] inputs. These RXMODE[1:0] inputs are only in-
terpreted when the decoder is enabled (DECMODE
≠
LOW).
These modes determine the type (if any) of channel bonding
and status reporting. The different receive modes are listed in
Table 21
.
Independent Channel Modes
In independent channel modes (RX Modes 0 and 2, where
RXMODE[1] = LOW), all four receive paths may be clocked in
any clock mode selected by RXCKSEL.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB
+
and RXCLKD
+
outputs are disabled
(High-Z), and the RXCLKA
+
and RXCLKC
+
outputs present a
buffered and delayed form of REFCLK. In this mode, the re-
ceive Elasticity Buffers are enabled. For REFCLK
↑
clocking,
the Elasticity Buffers must be able to insert K28.5 characters
and delete framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time on any channel, however, the actual timing
on these insertions and deletions is controlled in part by the
how the transmitter sends its data. Insertion of a K28.5 char-
acter can only occur when the receiver has a framing character
in the Elasticity Buffer. Likewise, to delete a framing character,
one must also be in the Elasticity Buffer. To prevent a receive
buffer overflow or underflow on a receive channel, a minimum
density of framing characters must be present in the received
data streams.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received to allow the receive Elasticity Buffer
to be centered. The Elasticity buffer may also be set by a de-
vice reset operation initiated through the TRSTZ input, howev-
er, following such an event the Frequency Agile PSI device will
normally require a framing event before it will correctly decode
characters.
When RXCKSEL is MID (or open), each received channel out-
put register is clocked by the recovered clock for that channel.
Since no characters may be added or deleted, the receiver
Elasticity Buffer is bypassed.
When RXCKSEL = HIGH, all channels are clocked by the se-
lected recovered clock. This selection is made using the
RXCLKB+ and RXCLKD+ signals as inputs per
Table 22
. This
selected clock is always output on RXCLKA
+
and RXCLKC
+
.
In this mode the receive Elasticity Buffers are enabled. When
data is output using a recovered clock (RXCKSEL = HIGH),
receive channels are not allowed to insert and delete charac-
ters, except as necessary for Elasticity Buffer alignment.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received to allow the receive Elasticity Buffers
to be centered. The Elasticity buffer may also be set by a de-
vice reset operation initiated through the TRSTZ input, howev-
er, following such an event the Frequency Agile PSI device will
normally require a framing event before it will correctly decode
characters. Since the Elasticity buffer is not allowed to insert
or delete framing characters, the transmit clocks on the chan-
nels must all be from a common source.
Dual-Channel Bonded Modes
In dual-channel bonded modes (RX Modes 3 and 5, where
RXMODE[1] = MID or open), the associated receive channel
pair output registers must be clocked by a common clock. This
mode does not operate when RXCKSEL = MID.
Proper operation in this mode requires that the associated
transmit data streams are clocked from a common reference
with no long-term character slippage between the bonded
channels. In dual-channel mode this means that channels A
and B must be clocked from a common reference, and chan-
nels C and D must be clocked from a common reference (all
four transmit channels
may
be clocked from the same source,
but that is not a requirement).
Prior to reception of valid characters, at least one Word Sync
Sequence (or that portion of one necessary to align the re-
ceive buffers) must be received on the bonded channels (with-
in the allowable inter-channel skew window) to allow the re-
Table 21. Receive Operating Modes
RX Mode
Operating Mode
M
N
R
[
Channel
Bonding
Independent
RXSTx Status Reporting
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
Status A
Reserved for test
Status B
0
1
2
3
4
5
6
7
8
LL
LM
LH
ML
MM
MH
HL
HM
HH
Independent
Dual
Dual
Quad
Quad
Table 22. Independent and Quad Channel Bonded
Recovered Clock Select
RXCLKB+
0
0
1
1
RXCLKD+
0
1
0
1
RXCLKA+/RXCLKC+
Clock Source
RXCLKA
RXCLKB
RXCLKC
RXCLKD
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