參數(shù)資料
型號(hào)： CYP15G0101
廠商： Cypress Semiconductor Corp.
英文描述： Single-channel HOTLink Transceiver
中文描述： 單通道的HOTLink收發(fā)器
文件頁(yè)數(shù)： 24/78頁(yè)
文件大小： 1555K
代理商： CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 24 of 78
ered character boundaries on any channel, regardless of the
presence of framing characters in the data stream.
10B/8B Decoder Block
The decoder logic block performs two primary functions:
decoding the received transmission characters back into
Data and Special Character codes,
comparing generated BIST patterns with received charac-
ters to permit at-speed link and device testing,
10B/8B Decoder
The framed parallel output of each deserializer shifter is
passed to the 10B/8B Decoder where, if the Decoder is en-
abled (DECMODE
≠
LOW), it is transformed from a 10-bit
transmission character back to the original Data and Special
Character codes. This block uses the 10B/8B decoder pat-
terns in
Tables 29
and
30
of this data sheet. Valid data char-
acters are indicated by a 000b bit-combination on the associ-
ated RXSTx[2:0] status bits, and Special Character codes are
indicated by a 001b bit-combination on these same status out-
puts. Framing characters, Invalid patterns, disparity errors, and
synchronization status are presented as alternate combina-
tions of these status bits.
The 10B/8B decoder operates in two normal modes, and can
also be bypassed. The operating mode for the decoder is con-
trolled by the DECMODE input.
When DECMODE = LOW, the decoder is bypassed and raw
10-bit characters are passed to the output register. In this
mode, channel bonding is not possible, the receive Elasticity
Buffers are bypassed, and RXCKSEL must be MID. This clock
mode generates separate RXCLKx
+
outputs for each receive
channel.
When DECMODE is MID (or open), the 10-bit transmission
characters are decoded using
Tables 29
and
30
. Received
Special Code characters are decoded using the Cypress col-
umn of
Table 30
.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using
Tables 29
and
30
. Received Special Code
characters are decoded using the Alternate column of
Table
30
.
In all settings where the decoder is enabled, the receive paths
may be operated as separate channels or bonded to form var-
ious multi-channel buses.
Receive BIST Operation
The receiver interfaces contain internal pattern generators that
can be used to validate both device and link operation. These
generators are enabled by the associated BOE[x] signals list-
ed in
Table 16
(when the BISTLE latch enable input is HIGH).
When enabled, a register in the associated receive channel
becomes a signature pattern generator and checker by logi-
cally converting to a Linear Feedback Shift Register (LFSR).
This LFSR generates a 511-character sequence that includes
all Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet pseudo-ran-
dom sequence that can be matched to an identical LFSR in
the attached Transmitter(s). When synchronized with the re-
ceived data stream, the associated receiver checks each char-
acter in the Decoder with each character generated by the
LFSR and indicates compare errors and BIST status at the
RXSTx[2:0] bits of the output register.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator/checker in the associated
receive channel (or the BIST generator in the associated trans-
mit channel). When BISTLE returns LOW, the values of all
BOE[x] signals are captured in the BIST Enable Latch. These
values remain in the BIST Enable Latch until BISTLE is re-
turned high to open the latch again. All captured signals in the
BIST Enable Latch are set HIGH (i.e., BIST is disabled) follow-
ing a device reset (TRSTZ is sampled LOW).
The LFSR is initialized by the BIST hardware once the BIST
enable for that receive channel is present at the output of the
BIST Enable Latch, and is recognized. This sets the BIST
LFSR to the BIST-loop start-code of D0.0 (D0.0 is sent only
once per BIST loop). The status of the BIST progress and any
character mismatches is presented on the RXSTx[2:0] status
outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXSTx[2:0] indicates 010b or 100b for one character period
per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. These same status values
are presented when the decoder is bypassed and BIST is en-
abled on a receive channel.
The specific status reported by the BIST state machine are
listed in
Table 26
. These same codes are reported on the re-
ceive status outputs regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note
“
HOTLink Built-In Self-
Test.
”
The sequence compared by the PSI transceiver block is
identical to that in the CY7B933 and CY7C924DX, allowing
interoperable systems to be built when used at compatible se-
rial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state ma-
chine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When the receive paths are configured for common clock op-
eration (RXCKSEL
≠
MID) each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer align-
ment and management of clock frequency variations. This is
automatically generated by the transmitter when its local
RXCKSEL
≠
MID.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the framer is en-
abled and configured for low-latency operation (RFMODE =
LOW), the framer can align to characters within the BIST se-
quence. If either of the multi-byte framers are enabled
(RFMODE
≠
LOW), it is generally necessary to frame the re-
ceiver before BIST is enabled. If the receive outputs are
clocked relative to REFCLK (RXCKSEL = LOW), the transmit-
ter precedes every 511 character BIST sequence with a 16-
character Word Sync Sequence. This sequence will frame the
receiver regardless of the setting of RFMODE.
Receive Elasticity Buffer
Each receive channel contains an Elasticity Buffer that is de-
signed to support multiple clocking modes. These buffers allow
data to be read using an Elasticity Buffer read-clock that is
asynchronous in both frequency and phase from the Elasticity
Buffer write clock, or to use a read clock that is frequency co-
herent but with uncontrolled phase relative to the Elasticity
Buffer write clock.
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