參數(shù)資料
型號(hào)： CYP15G0101
廠商： Cypress Semiconductor Corp.
英文描述： Single-channel HOTLink Transceiver
中文描述： 單通道的HOTLink收發(fā)器
文件頁(yè)數(shù)： 27/78頁(yè)
文件大小： 1555K
代理商： CYP15G0101
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 27 of 78
output register contains the selected framing character at the
proper character boundary, and LOW for all other bit combina-
tions.
When the low-latency framer and half-rate receive port clock-
ing are also enabled (RFMODE = LOW, RXRATE = HIGH, and
RXCKSEL
≠
LOW), the framer will stretch the recovered clock
to the nearest 20-bit boundary such that the rising edge of
RXCLKx+ occurs when COMDETx is present on the associat-
ed output bus.
When the standard framer is enabled and half-rate receive
port clocking are also enabled (RFMODE
≠
LOW and RXRATE
= HIGH), the output clock is not modified when framing is de-
tected, but a single pipeline stage may be added or subtracted
from the data stream by the framer logic such that the rising
edge of RXCLKx+ occurs when COMDET is present on the
associated output bus.
This adjustment only occurs when the framer is enabled
(RFEN = HIGH). When the framer is disabled, the clock bound-
aries are not adjusted, and COMDETx may be active during
the rising edge of RXCLKx
–
(if an odd number of characters
were received following the initial framing).
Receive Status Bits
When the 10B/8B decoder is enabled (DECMODE
≠
LOW),
each character presented at the output register includes three
associated status bits. These bits are used to identify
if the contents of the data bus are valid,
the type of character present,
the state of receive BIST operations (regardless of the state
of DECMODE),
character violations,
and channel bonding status
These conditions normally overlap; i.e., a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a decoder viola-
tion of some specific type. This implies a hierarchy or priority
level to the various status bit combinations. The hierarchy and
value of each status is listed in
Table 26
.
Table 24. Output Register Bit Assignments
Signal Name
RXSTx[2]
(LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
(MSB)
DECMODE = LOW
COMDETx
DOUTx[0]
DOUTx[1]
DOUTx[2]
DOUTx[3]
DOUTx[4]
DOUTx[5]
DOUTx[6]
DOUTx[7]
DOUTx[8]
DOUTx[9]
DECMODE = MID
or HIGH
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
Table 25. Decoder Bypass Mode (DECMODE = LOW)
Signal Name
RXSTx[2]
(LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
(MSB)
Bus Weight
COMDETx
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10B Name
a
b
c
d
e
i
f
g
h
j
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