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參數(shù)資料
| 型號(hào)： | CYP15G0101 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single-channel HOTLink Transceiver |
| 中文描述： | 單通道的HOTLink收發(fā)器 |
| 文件頁數(shù)： | 30/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 30 of 78
IEEE 1149.1 Compliant JTAG Operation
The PSI family has an IEEE std 1149.1 JTAG interface for both
Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The PSI family supports Bypass, Sample/Preload, Extest, In-
test, Idcode and Usercode boundary scan instructions. The
JTAG interface is shown in
Figure 15
.
Frequency Agile devices also allow system-level diagnosis of
transceiver interface and interconnect. Boundary scan is sup-
ported on the LVCMOS signals, inputs and outputs. The high-
speed serial inputs are not part of the JTAG test chain.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The PSI family implements ISR by providing a JTAG compliant
interface for on-board programming, robust routing resources
for pinout flexibility, and a simple timing model for consistent
system performance.
Configuration
The CPLD block in each device of the PSI family is designed
with Self-Boot capability. An embedded on-chip EEPROM is
used to store configuration data. For PSI devices, program-
ming is defined as the loading of a user
’
s design into the inter-
NO_SYNC
IN_SYNC
RESYNC
RXSTx=111
RESYNC_IN_SYNC
RXSTx=011
Reset
Figure 14. Status Type-B Receive State Machine
#
1
2
3
Condition
(BOND_INH = LOW OR Master Channel Did Not Bond) AND Deskew Window Expired
FRAMCHAR Detected
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error) OR ((BOND_INH = LOW
OR Master Channel Did Not Bond) AND (Deskew Window Expired))
Four Consecutive FRAMCHAR Detected
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid
Minus Valid = 4)
Last FRAMCHAR Before a Valid Character AND Bonded to Master Channel
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock)
Decoder Error
4
5
6
7
8
2
2
3
4
RXSTx = 101
5
RXSTx = 010
6
6
RXSTx = 010
RXSTx = 111
1
7
RXSTx = 101
8
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
| CYPOSIC2GVC-K | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYS25G0101DX | Physical Layer Devices |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBC | 制造商:Cypress Semiconductor 功能描述:PHY 1-CH 100-Pin TBGA |
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
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