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參數(shù)資料
| 型號(hào)： | CYP15G0101 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single-channel HOTLink Transceiver |
| 中文描述： | 單通道的HOTLink收發(fā)器 |
| 文件頁數(shù)： | 29/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G0101 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 29 of 78
characters are decoded directly. In RX Mode 0 the RESYNC
(111b) status is never reported. In RX Mode 2, neither the RE-
SYNC (111b) or Channel Lock Detected (010b) status are re-
ported.
Status Type-A Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
COULD_NOT_BOND, and IN_SYNC, as shown in
Figure 13
.
The IN_SYNC state can respond with multiple status types,
while others can respond with only one type.
Status Type-B Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
IN_SYNC, and COULD_NOT_BOND, as shown in
Figure 14
.
Some of these state can respond with only one status value,
while others can respond with multiple status types.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0]
bits identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Table
26
. When the receive PLL detects an out-of-lock condition, the
BIST state is forced to the Start-of-BIST state, regardless of
the present state of the BIST state machine. If the number of
detected errors ever exceeds the number of valid matches by
greater than 16, the state machine is forced to the
WAIT_FOR_BIST state where it monitors the interface for the
first character of the next BIST sequence (D0.0). Also, if the
Elasticity Buffer ever hits and overflow/underflow condition,
the status is forced to the BIST_START until the buffer is re-
centered (approximately nine character periods).
To ensure compatibility between the source and destination
BIST operating modes, the sending and receiving ends of the
BIST sequence must both have RXCKSEL = MID or both have
RXCKSEL
≠
MID.
NO_SYNC
RXSTx=101
IN_SYNC
RESYNC
RXSTx=111
COULD_NOT_BOND
RXSTx=101
Reset
Figure 13. Status Type-A Receive State Machine
#
1
2
3
4
5
State Transition Conditions
(BOND_INH = LOW) AND (Deskew Window Expired)
FRAMCHAR Detected
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Any Decoder Error)
Four Consecutive FRAMCHAR Detected
(Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR
(Invalid Minus Valid = 4)
Valid Character other than a FRAMCHAR
6
2
1
4
5
4
3
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
| CYPOSIC2GVC-K | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYS25G0101DX | Physical Layer Devices |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBC | 制造商:Cypress Semiconductor 功能描述:PHY 1-CH 100-Pin TBGA |
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
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