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參數(shù)資料
| 型號： | CYP15G0101 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single-channel HOTLink Transceiver |
| 中文描述： | 單通道的HOTLink收發(fā)器 |
| 文件頁數(shù)： | 22/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 22 of 78
transition density
range controls report the received data stream inside nor-
mal frequency range (±200 ppm)
receive channel enabled
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each re-
ceive channel, which changes synchronous to the selected
receive interface clock.
Analog Amplitude
While the majority of these signal monitors are based on fixed
constants, the analog amplitude level detection is adjustable
to allow operation with highly attenuated signals, or in high-
noise environments. This adjustment is made through the
SDASEL signal, a three-level select (ternary) input, which sets
the trip point for the detection of a valid signal at one of three
levels, as listed in
Table 18
. This control input effects the ana-
log monitors for all receive channels.
The Signal Detect monitors are active for the present line re-
ceiver, as selected by the associated INSELx input. When con-
figured for local loopback (LPEN = HIGH), no line receivers are
selected, and the LFI output for each channel reports only the
receive VCO frequency out-of-range and transition density
status of the associated transmit signal. When local loopback
is active, the analog amplitude monitors are disabled.
Transition Density
The transition detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received on
a channel (within the referenced period), the transition detec-
tion logic for that channel will assert LFIx. The LFIx output
remains asserted until at least one transition is detected in
each of three adjacent received characters.
Range Controls
The receive-VCO range-control monitors do more than just
report the frequency status of the received signal. They also
determine if the receive Clock/Data Recovery circuits (CDR)
should align the receive VCO clock to the data stream or to the
local REFCLK input. This function prevents the receive VCO
from tracking an out-of-specification received signal.
When the range-control monitor for a channel indicates that
the signaling rate is within specification, the phase detector in
the receive PLL is configured to track the transitions in the
received data stream. In this mode the LFIx output for the as-
sociated channel is HIGH (unless one of the other status mon-
itors indicates that the received signal is out of specification).
If the range-control monitor indicates that the received data
stream signaling-rate is out of specification, the phase detector
is configured to track the local REFCLK input, and the associ-
ated LFIx output is asserted LOW.
The specific trip points for this compare function are listed in
Table 19
. Because the compare function operates with two
asynchronous clocks, there is a small uncertainty in the mea-
surement. The switch points are asymmetric to provide hyster-
esis to the operation.
Receive Channel Enabled
The Frequency Agile PSI device contains four receive chan-
nels that can be independently enabled and disabled. Each
channel can be enabled or disabled separately through the
BOE[7:0] inputs, as controlled by the RXLE latch-enable sig-
nal. When RXLE is HIGH, the signals present on the BOE[7:0]
inputs are passed through the Receive Channel Enable latch
to control the PLLs and logic of the associated receive chan-
nel. The BOE[7:0] input associated with a specific receive
channel is listed in
Table 16
.
When RXLE is HIGH and BOE[x] is HIGH, the associated re-
ceive channel is enabled to receive and decode a serial stream
from the selected line receiver. When RXLE is HIGH and
BOE[x] is LOW, the associated receive channel is disabled and
internally configured for minimum power dissipation. If a single
channel of a bonded-pair or bonded-quad is disabled, this will
impact the ability of the receive channels to bond correctly. In
addition, if the disabled channel is selected as the master
channel for insert/delete functions, or for recovered clock se-
lect, these functions will not work correctly. Any disabled chan-
nel will indicate a constant /LFIx output. When RXLE returns
LOW, the values present on the BOE[7:0] inputs are latched in
the Receive Channel Enable Latch, and remain there until
RXLE returns HIGH to opened the latch again.
Note:
When a disabled receive channel is re-enabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate
for up to 10ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each receive channel. The clock
extraction function is performed by high-performance embed-
ded phase-locked loops (PLLs) that track the frequency of the
transitions in the incoming bit streams and align the phase of
their internal bit-rate clocks to the transitions in the selected
serial data streams.
Each CDR accepts a character-rate (bit-rate
÷
10) or half-
character-rate (bit-rate
÷
20) reference clock from the
REFCLK input. This REFCLK input is used to
Table 18. Analog Amplitude Detect Valid Signal Levels
SDASEL
LOW
MID (Open)
HIGH
Typical signal with peak amplitudes above
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Table 19. Receive Signaling Rate Range Control criteria
Current RX PLL
Tracking Source
Selected data
stream
(LFIx = HIGH)
Frequency
Difference
Between
Transmit Character
Clock & RX VCO
<1708 ppm
1708
–
1953 ppm
>1953 ppm
<488 ppm
488
–
732 ppm
>732 ppm
Next RX PLL
Tracking
Source
Data Stream
Indeterminate
REFCLK
Data Stream
Indeterminate
REFCLK
REFCLK
(LFIx = LOW)
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