
May 1997
77
DATA BOOK v1.5
BIT INDEX
CL-PS7110
Low-Power System-on-a-Chip
Numerics
64-Hz tick interrupt (TINT)
51
A
AC prescale
53
B
Battery low interrupt (BLINT)
50
Bit rate divisor
55
Bit to drive buzzer (BZTOG)
44
BOOT8BIT
47
BREAK
56
Buzzer Drive (BZMOD)
44
C
Clear to send (CTS)
46
Codec interface enable Rx (CDENRX)
44
Codec interface enable Tx (CDENTX)
44
Codec Rx FIFO empty (CRXFE)
47
Codec sound interrupt (CSINT)
50
Codec Tx FIFO full (CTXFF)
47
Cold start flag (CLDFLG)
46
D
Data carrier detect (DCD)
46
Data set ready (DSR)
46
Debug enable (DBGEN)
44
Display ID nibble (DID)
46
DRAM refresh enable (RFSHEN)
49
DRAM refresh rate (RFDIV)
50
Drive 0 from battery
54
Drive 0 from mains
54
Drive 1 pump ratio
54
E
Even parity (EVENPRT)
56
Expansion clock enable (CLKEN)
49
External expansion clock enable (EXCKEN)
44
External fast interrupt (EXTFIQ)
50
External interrupt input 1 (EINT1)
50
External interrupt input 2 (EINT2)
51
External interrupt input 3 (EINT3)
51
Extra stop (XSTOP)
56
F
FIFO buffering of Rx and Tx data enable (FIFOEN)
56
G
Grayscale enable (GSEN)
53
Grayscale mode (GSMD)
53
H
HP SIR protocol encoding enable (SIREN)
44
I
Internal UART enable (UARTEN)
44
Internal UART modem status changed interrupt
(UMSINT)
51
Internal UART receive FIFO half-full interrupt (URXINT)
51
Internal UART transmit FIFO half-empty interrupt
(UTXINT)
51
Inverted NDCDET enable (DCDET)
46
IrDA Tx mode (IRTXM)
45
K
Keyboard Scan
43
L
LCD enable bit (LCDEN)
44
Line length
52
M
Media changed direct read (MCDR)
46
Media changed interrupt (MCINT)
50
Microwire/SPI peripheral clock speed select
(ADCKSEL)
45
N
New battery flag (NBFLG)
46
P
Parity enable (PRTEN)
56
Pixel prescale
53
Power fail flag (PFFLG)
46
R
Reset flag (RSTFLG)
46
RTC compare match interrupt (RTCMI)
51
RTC divisor output (RTCDIV)
46
S
Sequential access enable (SQAEN)
49
BIT INDEX