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參數(shù)資料
| 型號(hào)： | CL-PS7110 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級(jí)晶片 |
| 文件頁數(shù)： | 73/82頁 |
| 文件大小： | 1101K |
| 代理商： | CL-PS7110 |
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May 1997
73
DATA BOOK v1.5
ELECTRICAL SPECIFICATIONS
CL-PS7110
Low-Power System-on-a-Chip
4.6.5
High-Z (System) Test Mode
This mode selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 0.
This test mode asynchronously disables all output buffers on the CL-PS7110; this has the effect of remov-
ing the CL-PS7110 from the PCB so that other devices on the PCB can be tested. The internal state of
the CL-PS7110 is not altered directly by this test mode.
4.6.6
Test ROM Mode
This mode is entered by holding the MEDCHG input high during the transition from low to high of the
NPOR input pin. If Test ROM mode is enabled the processor boots from an alternative 8-bit test ROM.
The effect of this test mode is to reverse the decoding for all expansion selects.
Table 4-7
shows this
decoding. In addition the sense of bit 1 in the Memory Configuration register is reversed so that 00 = 8-
bit access,
Table 4-7
lists the chip select address ranges, and
Table 4-8
, the bus width field combinations
during Test ROM mode. This has the effect of making the boot ROM an 8-bit device connected to CS7.
Table 4-7.
Chip Select Address Ranges During Test ROM Mode
Address Range
Expansion Chip Select in Test ROM Mode
0000.0000–0FFF.FFFF
CS7
1000.0000–1FFF.FFFF
CS6
2000.0000–2FFF.FFFF
CS5
3000.0000–3FFF.FFFF
CS4
4000.0000–4FFF.FFFF
NCS3
5000.0000–5FFF.FFFF
NCS2
6000.0000–6FFF.FFFF
NCS1
7000.0000–7FFF.FFFF
NCS0
Table 4-8.
Expansion and ROM Interface Bus Width During Test ROM Mode
Bus Width Field in ROM Test Mode
Expansion Transfer Mode
00
8-bit-wide bus access
01
PCMCIA mode
10
32-bit-wide bus access
11
16-bit-wide bus access
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相關(guān)代理商/技術(shù)參數(shù) |
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| CL-PS7110-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
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| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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