參數(shù)資料
型號(hào): CL-PS7110
廠商: Cirrus Logic, Inc.
英文描述: Low-Power System-on-a-Chip
中文描述: 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù): 62/82頁(yè)
文件大小: 1101K
代理商: CL-PS7110
DATA BOOK v1.5
May 1997
62
ELECTRICAL SPECIFICATIONS
CL-PS7110
Low-Power System-on-a-Chip
4.4
AC Characteristics
All characteristics are specified at
V
DD
= 3.0 to 3.6 volts and V
SS
= 0 volts over an operating temperature
of 0
°
C to +70
°
C. Parameters marked with an asterisk (*) are not fully tested.
Table 4-2.
AC Characteristics
Symbol
Parameter
MIN
MAX
Units
t
1
Falling CS to data bus High-Z
0*
25*
ns
t
2
Address change to valid write data
0
35
ns
t
3
DATA in to falling EXPCLK setup time
18
ns
t
4
DATA in to falling EXPCLK hold time
0
ns
t
5
EXPRDY to falling EXPCLK setup time
18
ns
t
6
Falling EXPCLK to EXPRDY hold time
0
50
ns
t
7
Rising NMWE to data invalid hold time
5
ns
t
8
Sequential data valid to falling NMWE setup time
10
10
ns
t
9
Row address to falling NRAS setup time
5
ns
t
10
Falling NRAS to row address hold time
25
ns
t
11
Column address to falling NCAS setup time
2
ns
t
12
Falling NCAS to column address hold time
25
ns
t
13
Write data valid to falling NCAS setup time
2
ns
t
14
Write data valid from falling NCAS hold time
50
ns
t
15
LCD CL2 low time
80
3,475
ns
t
16
LCD CL2 high time
80
3,475
ns
t
17
LCD Rising CL2 to rising CL1 delay
0
25
ns
t
18
LCD Falling CL1 to rising CL2
80
3,475
ns
t
19
LCD CL1 high time
80
3,475
ns
t
20
LCD Falling CL1 to falling CL2
200
6,950
ns
t
21
LCD Falling CL1 to FRM toggle
300
10,425
ns
t
22
LCD Falling CL1 to M toggle
10
20
ns
t
23
LCD Rising CL2 to display data change
10
20
ns
t
24
Falling EXPCLK to address valid
30
ns
t
25
Initial data valid to falling NMWE setup time
5
ns
t
EXTRD
Zero-wait-state memory read access time
70
ns
t
EXWR
Zero-wait-state memory write access time
70
ns
t
RC
DRAM cycle time
150
ns
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