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參數(shù)資料
| 型號： | CL-PS7110 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 70/82頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | CL-PS7110 |
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DATA BOOK v1.5
May 1997
70
ELECTRICAL SPECIFICATIONS
CL-PS7110
Low-Power System-on-a-Chip
4.5
I/O Buffer Characteristics
All I/O buffers on the CL-PS7110 are CMOS threshold input bidirectional buffers except the oscillator and
power pads. Notional input signals only enable the output buffer during Pin Test mode. All output buffers
are disabled during System Test (High-Z) mode. All buffers have a standard CMOS threshold input stage
apart from the Schmitt inputs and CMOS, slew-rate-controlled output stages to reduce system noise.
Table 4-3
defines the I/O buffer output characteristics.
NOTE:
1)
All propagation delays are specified at 50%
V
DD
to 50%
V
DD
; all rise times are specified as 10%
V
DD
to 90%
V
DD
,
and all fall times are specified as 90%
V
DD
to 10%
V
DD
.
Pull-up current = 50
μ
A typical at
V
DD
= 3.3 volts.
2)
4.6
Test Modes
The CL-PS7110 supports a number of hardware-activated test modes; these are activated by the pin
combinations shown in
Table 4-4
. All latched signals will only alter test modes while NPOR is low, and
their state is latched on the rising edge of NPOR. This allows these signals be used normally during var-
ious test modes; for example, the NURESET input can be used normally when the device is set into Func-
tional Test (EPB) mode.
Table 4-3.
I/O Buffer Output Characteristics
Buffer Type
Drive Current
Propagation Delay
(MAX)
Rise Time
(MAX)
Fall Time
(MAX)
Load
I/O strength 1
±
3 mA
15 ns
18 ns
15 ns
50 pF
I/O strength 2
±
3 mA
15 ns
15 ns
15 ns
50 pF
I/O strength 3
±
12 mA
12 ns
15 ns
13 ns
50 pF
I/O strength 4
±
12 mA
12 ns
180 ns
80 ns
1000 pF
Table 4-4.
CL-PS7110 Hardware Test Modes
Test Mode
Latched
MEDCHG
Latched
PE0
Latched
NURESET
NTEST0
NTEST1
Normal operation (32-bit boot)
0
0
X
1
1
Normal operation (8-bit boot)
0
1
X
1
1
Alternative test ROM boot
1
X
X
1
1
Oscillator/PLL bypass
X
X
X
1
0
Functional Test (EPB)
X
X
1
0
1
Oscillator/PLL Test
X
X
0
0
1
Pin Test
X
X
1
0
0
System Test (all High-Z)
X
X
0
0
0
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