參數(shù)資料
型號(hào)： CL-PS7110
廠商： Cirrus Logic, Inc.
英文描述： Low-Power System-on-a-Chip
中文描述： 低功耗系統(tǒng)級(jí)晶片
文件頁(yè)數(shù)： 48/82頁(yè)
文件大?。?/td> 1101K
代理商： CL-PS7110
DATA BOOK v1.5
May 1997
48
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
Table 3-7
defines the bus width field. Note that the effect of this field is dependent on the BOOT8BIT bit,
which can be read in the SYSFLG register. All bits in the Memory Configuration register are cleared by a
system reset and the state of the BOOT8BIT bit is determined by the Port E bit 0 pin on the CL-PS7110
during power-on reset. Pulling Port E bit 0 either low or high during power-on reset allows the CL-PS7110
to boot from either 32-bit-wide or 8-bit-wide ROMs.
When the bus width field is programmed to PCMCIA mode, the bus width and bus conversion is defined
by the state of A27 and A26.
Table 3-8
defines the bus width and bus conversion for values of A27 and
A26. Word bus conversion converts an ARM 32-bit word access into a series of byte or 16-bit accesses.
A special case is 16-bit I/O accesses (A26 and A27 high). In this case 32-bit ARM word accesses are not
converted into two 16-bit access, this allows individual 16-bit register access. In this mode, D16 to D31 is
invalid and the output expansion address bit 1 is selected by the value of A25. The CL-PS7110 always
outputs ‘0’ on expansion address bit 25, that is, in 16-bit I/O mode, processor address bit 25 becomes
PCMCIA address bit 1, and PCMCIA address bit 25 is ‘0’, limiting the 16-bit I/O address space to 32
Mbytes.
Table 3-7.
Values of the Bus Width Field
Bus Width
Field
BOOT8BIT
Expansion Transfer
Mode
Port E Bit 0 During Power-On
Reset
00
0
32-bit-wide bus access
Low
01
0
16-bit-wide bus access
Low
10
0
8-bit-wide bus access
Low
11
0
PCMCIA mode
Low
00
1
8-bit-wide bus access
High
01
1
PCMCIA mode
High
10
1
32-bit-wide bus access
High
11
1
16-bit-wide bus access
High
Table 3-8.
PCMCIA Mode Bus Width
A26
A27
Bus
Width
Word Bus
Conversion
PCMCIA Memory Area
0
0
8 bits
Yes
8-bit attribute memory access
1
0
16 bits
Yes
16-bit common memory access
0
1
8 bits
Yes
8-bit I/O access
1
1
16 bits
No
16-bit I/O access (see above)
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