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參數(shù)資料
| 型號： | CL-PS7110 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 44/82頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | CL-PS7110 |
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DATA BOOK v1.5
May 1997
44
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
TC1M
Timer Counter 1 (TC1) mode. Setting this bit sets TC1 to Prescale mode, clearing it
sets Free-running mode.
TC1S
Timer Counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz,
clearing it sets the clock source to 2 kHz.
TC2M
Timer Counter 2 (TC2) mode. Setting this bit sets TC2 to Prescale mode, clearing it
sets Free-running mode.
TC2S
Timer Counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz,
clearing it sets the clock source to 2 kHz.
UARTEN
Internal UART enable bit. Setting this bit enables the internal UART.
BZTOG
Bit to drive buzzer directly.
BZMOD
This bit sets the Buzzer Drive mode. 0 = the buzzer drive is connected directly to the
BZTOG bit. 1 = the buzzer drive is connected to the TC1 under-flow bit.
DBGEN
Setting this bit enables Debug mode. In this mode all internal accesses are output as
if they were reads or writes to expansion memory addressed by CS6. CS6 remains
active in its standard address range. In addition, the internal interrupt request and fast
interrupt request signals to the ARM710A microprocessor are output on port E bits 1
and 2 in Debug mode:
CS6 = CS6/internal I/O strobe
PE1 = NIRQ
PE2 = NFIQ
LCDEN
LCD enable bit. Setting this bit enables the LCD controller.
CDENTX
Codec interface enable Tx bit. Setting this bit enables the codec interface for data
transmission to an external codec device.
CDENRX
Codec interface enable Rx bit. Setting this bit enables the codec interface for data
reception from an external codec device.
SIREN
HP SIR protocol encoding enable bit. This bit has no effect if the UART is not enabled.
EXCKEN
External expansion clock enable. If this bit is set, the EXPCLK is enabled continu-
ously; it is the same speed and phase as the CPU clock, and free-run all the time the
main oscillator is running. This bit should not be left set for power consumption rea-
sons. If the system enters the standbystate, the EXPCLK is undefined. If this bit is
clear, EXPCLK is active during memory cycles to the expansion slots that have exter-
nal wait-state generation enabled.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7110-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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