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參數(shù)資料
| 型號： | CL-PS7110 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | 低功耗系統(tǒng)級晶片 |
| 文件頁數(shù)： | 47/82頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | CL-PS7110 |
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May 1997
47
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
CRXFE
Codec Rx FIFO empty bit. This is set if the 16-byte codec Rx FIFO is empty.
CTXFF
Codec Tx FIFO full bit. This is set if the 16-byte codec Tx FIFO is full.
SSIBUSY
Synchronous serial interface busy bit. This bit is set while data is shifted in or out of
the synchronous serial interface, when clear data is valid to read.
BOOT8BIT
This bit indicates the default (power-on reset) bus width of the ROM interface. If set,
the initial bus width is 8 bits, if clear it is 32 bits. See Memory Configuration Register
1 for more details on the ROM interface bus width. The state of this bit is determined
by the state of Port E bit 0 during power-on reset. LOW during power-on reset clears
the BOOT8BIT bit and the system boots from a 32-bit ROM, HIGH during power-on
reset sets the BOOT8BIT bit and the system boots from a 8-bit ROM.
Reserved
Write has no effect, always reads ‘0’.
VERID
Version ID bits. These two bits determine the version identification for the
CL-PS7110. Reads ‘0’ for the first version.
3.2.13 MEMCFG1 — Memory Configuration Register 1
Expansion and ROM space is selected by one of eight chip selects. Each chip select is active for 256
Mbytes and the timing and bus transfer width can be programmed individually. This is accomplished by
programming 8-byte-wide fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in
these registers are cleared by a system reset.
The Memory Configuration Register 1 is a 32-bit read/write register that sets the configuration of the four
expansion and ROM selects NCS0–NCS3. Each select is configured with a 1-byte field, starting with
expansion select 0.
3.2.14 MEMCFG2 — Memory Configuration Register 2
The Memory Configuration Register 2 is a 32-bit read/write register that sets the configuration of the four
expansion and ROM selects CS4–CS7. Each select is configured with a 1-byte field, starting with expan-
sion select 4.
Each of the eight byte fields in the Memory Configuration registers are identical and define the number of
wait states, the bus width, enable EXPCLK output during accesses and enable sequential mode access.
This byte field is defined below.
31
24
23
16
15
8
7
0
NCS3 configuration
NCS2 configuration
NCS1 configuration
NCS0 configuration
31
24
23
16
15
8
7
0
CS7 configuration
CS6 configuration
CS5 configuration
CS4 configuration
7
6
5
4
3
2
1
0
CLKEN
SQAEN
Sequential access wait state
Random access wait state
Bus width
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| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7110-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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