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參數(shù)資料
| 型號(hào)： | celeron CPU with Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器2（MMC管理- 2），466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器2處理器） |
| 文件頁數(shù)： | 31/47頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CELERON CPU WITH MOBILE MODULE |
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Celeron
Processor Mobile Module MMC-2
at 466 MHz and 433 MHz
27
4.7.2.1
Voltage Signal Definition and Sequencing
Table 21. Voltage Signal Definitions and Sequences
Source
Signal
Definitions and Sequences
V_DC
System Electronics
V_DC is required to be between 5V and 21V DC and is driven by the
system electronics’ power supply. V_DC powers the module’s DC-to-DC
converter for the processor core and I/O voltages. The module cannot be
hot inserted or removed while V_DC is powered on.
V_3
System Electronics
V_3 is supplied by the system electronics for the 82433BX.
V_5
System Electronics
V_5 is supplied by the system electronics for the 82433BX’s 5V-reference
voltage and the module’s voltage regulator.
VR_ON
System Electronics
VR_ON is a 3.3V (5V tolerant) signal that enables the module’s voltage
regulator circuit. When driven active high the voltage regulator circuit is
activated. The signal driving VR_ON should be a digital signal with a rise/fall
time of less than or equal to 1
μ
s.
(VIL (max)=0.4V, VIH (min)=3.0V).
V_CORE (also a
host bus GTL+
termination
voltage VTT)
Module
A result of VR_ON being asserted, V_CORE is an output of the DC-DC
regulator on the module and is driven to the core voltage of the processor. It
is also used as the host bus GTL+ termination voltage, known as VTT.
VR_PWRGD
Module
Upon sampling the voltage level of V_CORE (minus tolerances for ripple),
VR_PWRGD is driven active high. If VR_PWRGD is not sampled active
within 1 second of the assertion of VR_ON, then the system electronics
should deassert VR_ON. After V_CORE is stabilized, VR_PWRGD will
assert to logic high (3.3V). This signal
must not be pulled up
by the system
electronics. VR_PWRGD should be “ANDed” with V_3s to generate the
PIIX4E/M input signal, PWROK. The system electronics should monitor
VR_PWRGD to verify it is asserted high prior to the active high assertion
of PIIX4E/M PWROK.
V_CPUPU is 2.5V. The system electronics uses this voltage to power the
PIIX4E/M-to-processor interface circuitry.
V_CPUPU
Module
V_CLK
Module
V_CLK is 2.5V. The system electronics uses this voltage to power the
HCLK[0:1] drivers for the processor clock.
The following list provides additional specifications and clarifications of the power sequence timing and Figure 5 provides an
illustration.
1.
The VR_ON signal
may only be
asserted to a logical high by a digital signal
after
V_DC
≥
4.7 volts, V_5
≥
4.5
volts, and V_3
≥
3.0 volts.
The Rise Time and Fall Time of VR_ON
must
be less than or equal to
1 microsecond
when it goes through its Vil
to Vih.
VR_ON has its Vil (max) = +0.4 volts and Vih (min) = +3.0 volts.
The VR_PWRGD will get asserted to logic high (3.3 volts) after V_CORE is stabilized and V_DC reaches 5.0
volts. This signal should not and can not be pulled up by the system electronics.
In the power-on process, Intel recommends to raise the higher voltage power plane first (V_DC), followed by the
lower power planes (V_5, V_3), and finally assert VR_ON after above voltage levels are met on all rails. The
power-off process should be the reverse process, i.e. VR_ON gets deasserted, followed by the lower power
planes, and finally the higher power planes.
VR_ON must monotonically rise through its Vil to Vih and fall through its Vih to Vil points. The sign of slope can
not change between Vil and Vih in rising and Vih and Vil in falling.
VR_ON must provide an instantaneous in-rush current to the module with the following values as listed in Table
22.
2.
3.
4.
5.
6.
7.
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