- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379877 > celeron CPU with Mobile Module (Intel Corp.) processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) PDF資料下載
參數(shù)資料
| 型號： | celeron CPU with Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| 中文描述： | 移動處理器模塊連接器2（MMC管理- 2），466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器2處理器） |
| 文件頁數(shù)： | 10/47頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CELERON CPU WITH MOBILE MODULE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
Celeron
Processor Mobile Module MMC-2
at 466 MHz and 433 MHz
6
3.1.3
AGP (60 Signals)
Table 3 lists the AGP interface signals.
Table 3. AGP Signal Descriptions
Name
Type
Voltage
Description
GAD[31:0]
I/O
AGP
V_3
AGP Address/Data
: The standard AGP address and data lines. This bus functions in
the same way as the PCI AD[31:0] bus. The address is driven with FRAME# assertion
and data is driven or received in following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable
: This bus carries the command information during AGP
cycles when PIPE# is used. During an AGP write, this bus contains byte enable
information. The command is driven with FRAME# assertion and byte enables
corresponding to supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame
: Not used during AGP transactions. Remains deasserted by an internal
pullup resistor. Assertion indicates the address phase of a PCI transfer. Negation
indicates that the cycle initiator desires one more data transfer.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select
: Same function as PCI DEVSEL#. It is not used during AGP
transactions. The 82433BX Host Bridge system controller drives this signal when a PCI
initiator is attempting to access DRAM. DEVSEL# is asserted at medium decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready
: Indicates the AGP compliant target is ready to provide
all
write
data for the current transaction. Asserted when the initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready
: Indicates the AGP compliant master is ready to provide
all
write
data for the current transaction. Asserted when the target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop
: Same function as PCI STOP#. It is not used during AGP transactions.
Asserted by the target to request the master to stop the current transaction.
GREQ#
I
AGP
V_3
AGP Request
: AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant
: Same function as on PCI. Additional information is provided on the ST[2:0]
bus. PCI Grant: Permission is given to the master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity
: A single parity bit is provided over GAD[31:0] and GC/BE[3:0]. This signal
is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request
: Asserted by the current master to indicate a full width address that
is to be queued by the target. The master queues one request each rising clock edge
while PIPE# is asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address
: This bus provides an additional conduit to pass address and
commands to the 82433BX Host Bridge System Controller from the AGP master.
RBF#
I
AGP
V_3
Read Buffer Full
: Indicates if the master is ready to accept previously requested, low-
priority read data.
ST[2:0]
O
AGP
V_3
Status Bus
: Provides information from the arbiter to an AGP Master on what it may do.
These bits only have meaning when GGNT is asserted.
ADSTB[B:A]
I/O
AGP
V_3
AD Bus Strobes
: Provide timing for double-clocked data on the GAD bus. The agent
providing data drives these signals. These are identical copies of each other.
SBSTB
I
AGP
V_3
Sideband Strobe
: Provides timing for a sideband bus. The SBA[7:0] (AGP master)
drives the sideband strobe.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Celeron Processor with mobile | Celeron Processor Mobile Module MMC-1 at 400 MHz, 366 MHz, 333 MHz, and 300 MHz(工作頻率400,366,333,300和266兆赫茲帶移動模塊和連接器1處理器) |
| celeron processor | 32 bit Celeron Processor Mobile Module(32 位帶移動模塊處理器) |
| CEM11C2 | Dual Enhancement Mode Field Effect Transistor (N and P Channel) |
| CEM2005 | Dual Enhancement Mode Field Effect Transistor(N and Channel) |
| CEM2030A | Dual Enhancement Mode Field Effect Transistor(N and P Channel) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CELF001001J1 | 制造商:Panasonic Industrial Company 功能描述:FILTER |
| CELHK11-1REC5-59-3.00-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 3A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:3A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-59-35.0-AV-01-V | 功能描述:CIRCUIT BRKR MAG-HYDR LEVER 35A 制造商:sensata technologies/airpax 系列:CEL 零件狀態(tài):有效 斷路器類型:磁性（液力延遲） 額定電流:35A 額定電壓 - AC:- 額定電壓 - DC:- 極數(shù):2 致動器類型:搖臂 照明:- 照明電壓（標(biāo)稱值）:- 安裝類型:面板安裝 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-10-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
| CELHK11-1REC5-71165-11-V | 功能描述:CIRCUIT BREAKER MAG-HYDR LEVER 制造商:sensata technologies/airpax 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。