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參數(shù)資料
| 型號(hào)： | celeron CPU with Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器2（MMC管理- 2），466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器2處理器） |
| 文件頁數(shù)： | 15/47頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CELERON CPU WITH MOBILE MODULE |
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Celeron
Processor Mobile Module MMC-2
at 466 MHz and 433 MHz
11
3.1.8
Clock (9 Signals)
Table 8 lists the clock signals.
Table 8. Clock Signal Descriptions
Name
Type
Voltage
Description
PCLK
I
PCI
V_3
PCI Clock In:
PCLK is an input to the module and is one of the system’s PCI clocks.
This clock is used by all of the 82433BX Host Bridge logic in the PCI clock domain.
This
clock is stopped when the PIIX4E/M PCI_STP# signal is asserted and/or during all
suspend states.
HCLK[1:0]
I
CMOS
V_CLK
Host Clock In:
These clocks are inputs to the module from the CK97-M clock source.
The processor and the 82433BX Host Bridge system controller use HCLK[0]. This clock
is stopped when the PIIX4E/M CPU_STP# signal is asserted and/or during all suspend
states.
DCLKO
O
CMOS
V_3
SDRAM Clock Out:
A 66-MHz SDRAM clock reference generated internally by the
82433BX Host Bridge system controller onboard PLL. It feeds an external buffer that
produces multiple copies for the SO-DIMMs.
DCLKRD
I
CMOS
V_CLK
SDRAM Read Clock:
Feedback reference from the SDRAM clock buffer. The 82433BX
Host Bridge System Controller uses this clock when reading data from the SDRAM
array. This signal is not implemented on the module.
DCLKWR
I
CMOS
I
CMOS
O
CMOS
V_CLK
SDRAM Write Clock:
Feedback reference from the SDRAM clock buffer. The 82433BX
Host Bridge system controller uses this clock when writing data to the SDRAM array.
GCLKIN
V_3
AGP Clock In:
The GCLKIN input is a feedback reference from the GCLKO signal.
GCLKO
V_3
AGP Clock Out:
This signal is generated by the 82433BX Host Bridge system controller
onboard PLL from the HCLK0 host clock reference. The frequency of GCLKO is 66
MHz. The GCLKO output is used to feed both the PLL reference input pins on the
82433BX Host Bridge system controller and the AGP device. The board layout must
maintain complete symmetry on loading and trace geometry to minimize AGP clock
skew.
FQS
O
CMOS
V_CLK
Frequency Select:
This output signal provides the status of the host clock frequency to
the system electronics.
This signal is static and is pulled either low or high to the V_CLK
voltage supply through a 10-K
resistor. This module is designed for the 66-MHz
strapping option shown below.
FQS=0 indicates 66 MHz
FQS=1 indicates 100 MHz (for future Intel mobile modules)
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