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參數(shù)資料
| 型號(hào)： | celeron CPU with Mobile Module |
| 廠商： | Intel Corp. |
| 英文描述： | processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器) |
| 中文描述： | 移動(dòng)處理器模塊連接器2（MMC管理- 2），466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器2處理器） |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CELERON CPU WITH MOBILE MODULE |
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Celeron
Processor Mobile Module MMC-2
at 466 MHz and 433 MHz
8
3.1.5
Geyserville (4 Signals)
Table 5 lists the Geyserville signal definitions. The Celeron
processor mobile module MMC-2 does not support
Geyserville technology.
Table 5. Geyserville Descriptions
Name
Type
Voltage
Description
G_LO/HI#
I
CMOS
V_3
Geyserville State Transition
: Generated by the PIIX4E/M, this signal defines a Geyserville
state change to the Geyserville state machine. This signal is not implemented on the
module and is defined for upgrade purposes only.
G_CPU_STP#
I
CMOS
V_3
Geyserville CPU_STP#
: The CPU_STP# signal gated by the Geyserville state machine
becomes G_CPU_STP#. This signal is not implemented on the module and is defined for
upgrade purposes only.
VRCHGNG#
O
CMOS
V_3
Voltage Changing
: A Geyserville state machine signal that indicates that the actual state
change is in progress – the VR setpoint has changed and the VR is settling. When this
signal deasserts, the new state is sent to the processor. The system electronics will use this
signal to generate an SCI to force a transition out of deep sleep. This signal is not
implemented on the module and is defined for upgrade purposes only.
G_SUS_STAT1#
O
CMOS
V_3
G_SUS_STAT1#:
The SUS_STAT1# signal gated by the Geyserville control logic.
G_SUS_STAT1# should be used in place of the SUS_STAT1# signal in the system
electronics design. This signal is not implemented on module and is defined for upgrade
purposes only.
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