參數(shù)資料
型號(hào)： celeron CPU with Mobile Module
廠商： Intel Corp.
英文描述： processor Mobile Module Connector 2 (MMC-2) at 466 MHz and 433MHZ(工作頻率466和433兆赫茲帶連接器2處理器)
中文描述： 移動(dòng)處理器模塊連接器2（MMC管理- 2），466 MHz和433MHz的（工作頻率466和433兆赫茲帶連接器2處理器）
文件頁(yè)數(shù)： 23/47頁(yè)
文件大?。?/td> 410K
代理商： CELERON CPU WITH MOBILE MODULE
Celeron
Processor Mobile Module MMC-2
at 466 MHz and 433 MHz
19
Table 14. Configuration Straps for the 82433BX Host Bridge System Controller
Function
Module Default Setting
Signal
Optional Override on
System Electronics
MAB[12]#
Host Frequency
Select
No strap
66 MHz default.
None
MAB[11]#
In Order Queue
Depth
No strap
maximum queue depth is
set, i.e. 8.
None
MAB[10]
Quick Start Select
Strapped high on the module for
Quick Start mode.
None
MAB[9]#
AGP disable
No strap
AGP is enabled.
Pull up this signal to disable
the AGP interface.
MAB[7]#
MM Config
No strap
standard MMC-2 mode.
None
MAB[6]#
Host Bus Buffer
Mode Select
Strapped high on the module for
mobile PSB buffers.
None
4.3.3
PCI Interface
The PCI interface of the 82433BX Host Bridge is available at
the connector. The 82433BX Host Bridge supports the PCI
Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain
signal when they require the use of the PCI interface. Refer
to the
PCI Mobile Design Guide
for complete details on the
PCI Clockrun protocol.
The 82433BX Host Bridge is responsible for arbitrating the
PCI bus. With the MMC-2 connector, the 82433BX Host
Bridge can support up to five PCI bus masters. There are
five PCI Request/Grant pairs, REQ[4:0]# and GNT[4:0]#,
available on the connector to the manufacturer’s system
electronics.
The PCI interface on the MMC-2 connector is 3.3 volts only.
Five-volt PCI devices are not supported such as all devices
that drive outputs to a 5
Vt
nominal V
oh
level.
The 82433BX Host Bridge system controller is compliant
with the
PCI 2.1 specification
, which improves the worst
case PCI bus access latency from earlier PCI specifications.
The 82433BX Host Bridge supports only Mechanism #1 for
accessing PCI configuration space, as detailed in the PCI
specification. This implies that signals AD[31:11] are
available for PCI IDSEL signals. However, since the
82433BX Host Bridge is always device #0, AD11 will never
be asserted during PCI configuration cycles as an IDSEL.
The 82433BX reserves AD12 for the AGPbus. Thus, AD13 is
the first available address line usable as an IDSEL. Intel
recommends that AD18 be used by the PIIX4E/M.
4.3.4
AGP Interface
The 82433BX Host Bridge system controller is compliant
with the
AGP Interface Specification Rev 1.0
, which supports
only an asynchronous AGP interface coupling to the
82433BX core frequency. The AGP interface can achieve
real data throughput in excess of 500 megabytes per second
using an AGP 2X graphics device. Actual bandwidth may
vary depending on specific hardware and software
implementations.
4.4
Power Management
4.4.1
Clock Control Architecture
The clock control architecture is optimal for notebook
designs. The clock control architecture consists of seven
different clock states: Normal, Stop Grant, Auto Halt, Quick
Start, HALT/Grant Snoop, Sleep, and Deep Sleep states.
The Auto Halt state provides a low-power clock state that
can be controlled through the software execution of the HLT
instruction. The Quick Start state provides a very low-power,
low-exit latency clock state that can be used for hardware
controlled “idle” states. The Deep Sleep State provides an
extremely low power state that can be used for “Power-on
Suspend” states, which is an alternative to shutting off the
processor’s power. The exit latency of the Deep Sleep State
has been reduced to 30 microseconds. The Stop Grant and
Sleep states are not available on the Celeron processor
mobile module as these states are intended for desktop or
server systems. The Stop Grant state and the Quick Start
clock state are mutually exclusive. For example, a strapping
option on signal A15# chooses which state is entered when
the STPCLK# signal is asserted. Strapping the A15# signal
enables the Quick Start state to ground at Reset. Otherwise,
asserting the STPCLK# signal puts the processor into the
Stop Grant state. The Stop Grant state is useful for SMP
platforms and is not supported on the Celeron processor
mobile module. The Quick Start state is available on the
module and provides a significantly lower power level.
Figure 3 provides an illustration of the clock control
architecture. State transitions not shown in Figure 3 are
neither recommended nor supported
相關(guān)PDF資料
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