參數(shù)資料
型號： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 9/160頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設(shè)備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
14
4341H–MP3–10/07
AT8xC51SND2C/MP3B
5.2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle, the
AT8xC51SND2C need only 6 oscillator clock periods per machine cycle. This feature called the
“X2 feature” can be enabled using the X2 bit(1) in CKCON (see Table 5-1) and allows the
AT8xC51SND2C to operate in 6 or 12 oscillator clock periods per machine cycle. As shown in
Figure 5-1, both CPU and peripheral clocks are affected by this feature. Figure 5-3 shows the X2
mode switching waveforms. After reset the standard mode is activated. In standard mode the
CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it
is the oscillator frequency.
Note:
1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see Table 6-3
on page 22). Using the AT89C51SND2C (Flash Version) the system can boot either in stan-
dard or X2 mode depending on the X2B value. Using AT83SND2C (ROM Version) the system
always boots in standard mode. X2B bit can be changed to X2 mode later by software.
Figure 5-3.
Mode Switching Waveforms
Note:
1. In order to prevent any incorrect operation while operating in X2 mode, user must be aware
that all peripherals using clock frequency as time reference (timers, etc.) will have their time
reference divided by 2. For example, a free running timer generating an interrupt every 20 ms
will then generate an interrupt every 10 ms.
5.3
PLL
5.3.1
PLL Description
The AT8xC51SND2C PLL is used to generate internal high frequency clock (the PLL Clock) syn-
chronized with an external low-frequency (the Oscillator Clock). The PLL clock provides the MP3
decoder, the audio interface, and the USB interface clocks. Figure 5-4 shows the internal struc-
ture of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock com-
ing from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Table 5-2) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-
ing or extracting charges from the external filter connected on PFILT pin (see Figure 5-5). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref produced by the
charge pump. It generates a square wave signal: the PLL clock.
X1 ÷ 2
X1
Clock
X2 Bit
X2 Mode(1)
STD Mode
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