參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 15/160頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
5-19
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
PLL1_X2FBD2:
These 6 register bits set the first feedback divider bits for
PLL1. On power-on-reset the value is set to 000111b (7
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL1_X1FBD1:
These 5 register bits set the second feedback divider bits
for PLL1. On power-on-reset the value is set to 10011b (19
decimal).
Note: The value in the register is the actual coefficient minus one.
PLL1_PS:
These two bits determine the final divide on the VCO clock
signal in PLL1.
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset these bits are reset to 11b (3 decimal).
Note: This means that PLL1 FOUT is programmed to be 36,864,000 Hz on startup.
Note: The value in the register is the actual coefficient minus one.
PCLKDIV:
These two bits set the divide ratio between the HCLK AHB
clock and the APB clock (PCLK)
00 - Divide by 1
01 - Divide by 2
10 - Divide by 4
11 - Divide by 8
On power-on-reset the value is set to 00b.
Note: Care must be taken to make the correct selection of PCLK divide for the HCLK frequency
used, so that the required minimum ratio between PCLK and the peripheral clock is not
violated
HCLKDIV:
These three bits set the divide ratio between the VCO
output and the bus clock (HCLK)
000 - Divide by 1
100 - Divide by 6
001 - Divide by 2
101 - Divide by 8
010 - Divide by 4
110 - Divide by 16
011 - Divide by 5
111 - Divide by 32
On power-on-reset the value is set to 000b.
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