參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 39/160頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
6-5
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
6
TC1UI
Timer Counter 1 Under Flow Interrupt. When Timer
Counter 1 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
TC2UI
Timer Counter 2 Under Flow Interrupt. When Timer
Counter 2 has underflowed (reached zero), this interrupt
becomes active on the next falling edge of the timer’s
clock. The interrupt is cleared by writing any value to the
AACINTR
Advanced Audio CODEC Interrupt. See Chapter 22,
DMAM2P0
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 0 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P1
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 1 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P2
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 2 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P3
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 3 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P4
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 4 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P5
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 5 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P6
Internal Memory-to-peripheral and Peripheral-to-memory
Channel 6 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P7
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 7 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P8
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 8 Interrupt. See Chapter 10, "DMA Controller".
DMAM2P9
Internal Memory-to-Peripheral and Peripheral-to-Memory
Channel 9 Interrupt. See Chapter 10, "DMA Controller".
DMAM2M0
Memory-to-Memory (incorporating external M2P/P2M)
Channel 0 Interrupt. See Chapter 10, "DMA Controller".
DMAM2M1
Memory-to-Memory (incorporating external M2P/P2M)
Channel 1 Interrupt. See Chapter 10, "DMA Controller".
UART1RXINTR1
UART 1 Receive Interrupt. See Chapter 14, "UART1 With
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