參數(shù)資料
型號： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 16/160頁
文件大小： 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
5-20
DS785UM1
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
nBYP1:
This bit selects the clock source for the processor clock
dividers. With this bit clear, the system wakes up and
boots with the PLL bypassed and uses an external clock
source. With nBYP1 set, the system runs with the PLL
generated clock. The default for this bit is to boot/run from
external clock source.
SMCROM:
If set, this bit will gate off the HCLK to the Static Memory
Controller when in Halt mode and therefore save power.
When in Halt mode, there are no Instruction Code fetches
occurring and therefore if there are no DMA operations in
progress that may require the SMC, there will be no
accesses to this controller. It may therefore be safely
disabled when in Halt mode. This bit is 0b on reset.
FCLKDIV:
These three bits set the divide ratio between the VCO
output and processor clock. On power-on-reset the value
is set to 000b.
000 - Divide by 1
011 - Divide by 8
001 - Divide by 2
100 - Divide by 16
010 - Divide by 4
For FCLKDIV values equal to 1xxb (except for 100b), the
divide ratio will be divide by 1.
ClkSet2
Address:
0x8093_0024 - Read/Write
Definition:
The ClkSet2 register is used for setting the dividers internally to PLL2 and to
the USB Host divider. The reset setting for PLL2 creates a frequency of
48 MHz. The default divider for USB_DIV is divide by 1, which will produce the
USB host clock frequency and FIR clock frequency of 48 MHz.
Bit Descriptions:
PLL2_X2IPD:
These 5 register bits set the input divider for PLL2
operation. On power-on-reset the value is set to 10111b
(23 decimal).
Note: The value in the register is the actual coefficient minus one.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
USB DIV
RSVD
nBYP2
PLL2_EN
PLL2_PS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PLL2 X1FBD1
PLL2 X2FBD2
PLL2 X2IPD
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相關代理商/技術參數(shù)
參數(shù)描述
AT89C51-W 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C52 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
AT89C52_00 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52_99 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52-12AA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
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