參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 19/160頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
5-23
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
BusMstrArb
Address:
0x8093_0054 - Read/Write
Definition:
The Bus Master arbitration register (BusMstrArb) is used to configure the AHB
master priority order.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
PRI_ORD:
Used to set the priority of the AHB arbiter. The priority
order is shown in Table 5-6. This field resets to 00.
PRI_CORE:
When this bit is set the Core will become highest priority
following a grant to one of the following: Raster, Raster
Cursor, MAC, USB and DMA. If the Core then requests the
bus, it is then placed in the priority order selected by
PRI_ORD after it is granted, until one of the above
masters is granted the bus, and is placed on top of the
priority scheme.
DMA_ENIRQ:
When set the arbiter will degrant DMA from the AHB bus
and will ignore subsequent requests from DMA if an IRQ is
active. When IRQ is cleared the DMA request is allowed
again. There is no impact on other masters. Reset to 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
987654
3210
RSVD
MAC
ENFIQ
MAC
ENIRQ
USH
ENFIQ
USH
ENIRQ
DMA_
ENFIQ
DMA_
ENIRQ
PRI
CORE
RSVD
PRI_ORD
Table 5-6. Priority Order for AHB Arbiter
Priority Number
PRIOR 00
(Reset value)
PRIOR 01
PRIOR 10
PRIOR 11
1
Raster Cursor
Raster
2
MAC
Raster Cursor
DMA
3
USB
MAC
DMA
MAC
4
DMA
USB
5
ARM920T
MAC
Raster Cursor
6
Raster
DMA
ARM920T
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