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參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 35/160頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
6-1
Copyright 2007 Cirrus Logic
6
Chapter 6
6Vectored Interrupt Controller
6.1 Introduction
The EP93xx processors contain two cascaded Vectored Interrupt Controllers (VIC). A
Vectored Interrupt has improved latency compared with a simple interrupt controller, since it
provides direct information about where the interrupt’s service routine is located and
eliminates levels of software arbitration.
Each individual Vectored Interrupt Controller can handle up to 32 interrupts, but there are
more than 32 interrupts in this design. Therefore two VICs are connected in a daisy-chain,
which allows the system to handle up to 64 interrupt sources.
There are up to 16 vectored interrupts and 16 non-vectored interrupts available on each VIC.
Vectored interrupts can only generate an IRQ interrupt. Non-vectored interrupts can generate
either an IRQ interrupt or a FIQ interrupts. Vectored Interrupt Requests (IRQ) provide an
address for an Interrupt Service Routine (ISR). Reading from the vector interrupt address
register, VICxVectAddr, provides the address of the ISR, and indicates to the interrupt priority
hardware that the interrupt is being serviced. Writing to the VICxVectAddr register indicates
to the interrupt priority hardware that the interrupt has been serviced, allowing lower priority
interrupts to go active.
Registers in the VIC use a bit position for each different interrupt source. The bit position is
fixed, but the handling of each interrupt is configurable by the VIC. Software can generate
software interrupts by controlling each request line.
The VIC provides a software interface to the interrupt system. Two levels of interrupts are
available:
Fast Interrupt Request (FIQ) for fast, low latency interrupt handling
Interrupt Request (IRQ) for more general interrupts
All interrupt inputs to the VIC are presented as active-high level sensitive signals. Any
conditioning needed to achieve this is performed by the block generating the interrupt
request. In the case of external interrupts, the GPIO block takes care of the conditioning.
Note: Some GPIO signals are not configurable but are used as inputs by other functional
blocks. EGPIO[2:1] are routed to the DMA controller to allow for external DMA requests.
Note: An interrupt vector may be overwritten when two interrupts occur simultaneously. If a
VIC2 interrupt is immediately followed by a VIC1 interrupt, the VIC1 address will
incorrectly be the default handler address for 2 HCLK cycles. To work around this
problem, first check for pending non-vectored VIC1 interrupts in the interrupt routine. If
there are none then return from interrupt. The interrupt will immediately re-occur with the
correct vector address.
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