參數(shù)資料
型號： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 6/160頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設(shè)備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
DS785UM1
5-11
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
Figure 5-4. Power States and Transitions
5.1.6.2.1
Power-on-Reset Run
After power-on-reset, the ARM Core is automatically in run mode.
5.1.6.2.2
Run Standby Mode
Once in run mode, it is possible to move to the Standby state under these conditions:
A read from the Standby register location 0x8093_000C when the SHena bit in the
"DeviceCfg" register is set to 1. This triggers the system to enter STANDBY mode.
A write to the "ClkSet1" register.
When the SHena bit is set to 1 and the user reads the Standby register location
0x8093_000C, the EP93xx is forced to transition into the Standby state. After this transition,
the state controller will hold the Standby state before re-loading and allowing transition to the
Run state.
A write to the "ClkSet1" register will also trigger the system to go into Standby mode.
However, the system will automatically come back to normal operation after new clock
settings take effect. The amount of time the EP93xx remains in the Standby state depends on
whether the PLL is enabled, or if the EP93xx is using the external clock. If the PLL is enabled,
the EP93xx will remain in Standby until the PLL is locked. If the EP93xx is in PLL bypass
mode (nBYP1 = 1), then the EP93xx will remain in the Standby state for One to two
16.384 kHz clock cycles. This is to ensure a minimum 'off' time. The 16.384 kHz clock,
derived from the 32.768 kHz clock, times how long the EP93xx remains in the Standby state.
When the EP93xx normally enters Standby mode, the SDRAM controller puts the external
SDRAM into self-refresh before disabling its clocks (see “SDRAM Self Refresh” on page 13-
8). This condition is only true if the refresh enable bit (RFSHEN) in the SDRAM controller is
Interrupt (if enabled) or
return from ClkSet1
Power on
Reset
Standby
Run
Halt
Write to
ClkSet1 register
Read Standby register &
SHena = 1
Any Enabled Interrupt
Read Halt register
& SHena = 1
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參數(shù)描述
AT89C51-W 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89C52 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
AT89C52_00 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52_99 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52-12AA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
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