參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 102/160頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
7-41
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
VClkStrtStop
Address: 0x8003_000C
Default: 0x0000_0000
Definition: Vertical Clock Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP timing register contains the value of the Vertical
down counter at which the VCLKEN signal goes inactive
(stops). This indicates the end of the video clock for the
Vertical frame. Please refer to video signalling timing
diagrams in Figure 7-9 and Figure 7-10. VCLKEN is an
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
STRT:Start - Read/Write
The STRT timing register contains the value of the Vertical
down counter at which the VCLKEN signal becomes
active (starts). This indicates the start of the video clock for
the Vertical frame. Please refer to video signalling timing
diagrams in Figure 7-9 and Figure 7-10. VCLKEN is an
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
STOP
15
14
13
12
11
10
987654
3210
RSVD
STRT
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