參數(shù)資料
型號: ADUC7021BCPZ62-RL7
廠商: Analog Devices Inc
文件頁數(shù): 85/92頁
文件大?。?/td> 0K
描述: IC MCU 12BIT 1MSPS UART 40-LFCSP
標(biāo)準(zhǔn)包裝: 750
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PLA,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 86 of 92
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC7019/20/21/22/24/25/26/27/28. For LVDD below 2.35 V
typical, the internal POR holds the part in reset. As LVDD rises
above 2.35 V, an internal timer times out for typically 128 ms
before the part is released from reset. The user must ensure that
the power supply IOVDD has reached a stable 2.7 V minimum
level by this time. Likewise, on power-down, the internal POR
holds the part in reset until LVDD has dropped below 2.35 V.
Figure 81 illustrates the operation of the internal POR in detail.
04
95
5-
05
0
IOVDD
3.3V
2.6V
2.35V TYP
128ms TYP
LVDD
POR
RST
0.12ms TYP
Figure 81. Internal Power-On Reset Operation
TYPICAL SYSTEM CONFIGURATION
A typical ADuC7020 configuration is shown in Figure 82. It summarizes some of the hardware considerations discussed in the previous
sections. The bottom of the CSP package has an exposed pad that needs to be soldered to a metal plate on the board for mechanical
reasons. The metal plate of the board can be connected to ground.
NOT CONNECTED IN THIS EXAMPLE
30
29
28
27
26
25
XCLKI
24
XCLKO
23
22
21
1
2
3
GNDREF
4
DAC0
5
6
7
8
TMS
9
TDI
10
P0.0
40
39
38
ADC0
37
AV
DD
36
AG
ND
35
V
RE
F
34 33
P1
.0
32
P1
.1
31
11
12
13
TD
O
TC
K
14
IOG
N
D
15
IOV
DD
16
LV
DD
DG
ND
17 18
TR
S
T
19
RS
T
20
DVDD
1k
10
ADuC7020
0.01F
+
AVDD 0.47F
TDO
TCK
TMS
TDI
TRST
JT
AG
CO
NN
E
C
T
O
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVDD
100k
100k
100k
DVDD
32.768kHz
0.47F
1k
0.1F
10F
1.5
270
DVDD
AVDD
ADP3333-3.3
IN
OUT
SD
GND
1
C1+
2
V+
3
C1–
4
C2+
5
C2–
6
V–
7
T2OUT
8
R2IN
ADM3202
RS232 INTERFACE*
*EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
STANDARD D-TYPE
CONNECTOR TO
PC HOST
16
VCC
15
GND
14
T1OUT
13
R1IN
12
R1OUT
11
T1IN
10
T2IN
9
R2OUT
1
2
3
4
5
6
7
8
9
04
95
5-
051
Figure 82. Typical System Configuration
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