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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 59 of 92
The GDCLK value can range from 0 to 255, corresponding to a
programmable chopping frequency rate of 40.8 kHz to 10.44 MHz
for a 41.78 MHz core frequency. The gate drive features must be
programmed before operation of the PWM controller and are
typically not changed during normal operation of the PWM
controller. Following a reset, all bits of the PWMCFG register
are cleared so that high frequency chopping is disabled, by default.
049
55
-03
1
PWMCH0
PWMDAT0
0L
0H
2 × PWMDAT1
4 × (GDCLK + 1) ×
tCORE
2 × PWMDAT1
Figure 61. Typical PWM Signals with High Frequency Gate Chopping
Enabled on Both High-Side and Low-Side Switches
PWM Shut Down
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the off state, that is, in low state. In addition, the
PWMSYNC pulse is disabled. The PWMTRIP pin has an internal
pull-down resistor to disable the PWM if the pin becomes
disconnected. The state of the PWMTRIP pin can be read from
Bit 3 of the PWMSTA register.
If a PWM shutdown command occurs, a PWMTRIP interrupt is
generated, and internal timing of the 3-phase timing unit of the
PWM controller is stopped. Following a PWM shutdown, the
PWM can only be re-enabled (in a PWMTRIP interrupt service
routine, for example) by writing to all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers. Provided that
the external fault is cleared and the PWMTRIP is returned to a
high level, the internal timing of the 3-phase timing unit
resumes, and new duty-cycle values are latched on the next
PWMSYNC boundary.
Note that the PWMTRIP interrupt is available in IRQ only,
and the PWMSYNC interrupt is available in FIQ only. Both
interrupts share the same bit in the interrupt controller.
Therefore, only one of the interrupts can be used at once.
See the Interrupt System section for further details.
PWM MMRs Interface
The PWM block is controlled via the MMRs described in
this section.
PWMCON Register
Name
Address
Default Value
Access
PWMCON
0xFFFFFC00
0x0000
R/W
PWMCON is a control register that enables the PWM and
chooses the update rate.
Table 36. PWMCON MMR Bit Descriptions
Bit
Name
Description
7:5
–
Reserved.
4
PWM_SYNCSEL
External Sync Select. Set to use external
sync. Cleared to use internal sync.
3
PWM_EXTSYNC
External Sync Select. Set to select
external synchronous sync signal.
Cleared for asynchronous sync signal.
2
PWMDBL
Double Update Mode. Set to 1 by user
to enable double update mode.
Cleared to 0 by the user to enable
single update mode.
1
PWM_SYNC_EN
PWM Synchronization Enable. Set by
user to enable synchronization. Cleared
by user to disable synchronization.
0
PWMEN
PWM Enable Bit. Set to 1 by the user
to enable the PWM. Cleared to 0 by
the user to disable the PWM. Also
cleared automatically with PWMTRIP.
PWMSTA Register
Name
Address
Default Value
Access
PWMSTA
0xFFFFFC04
0x0000
R/W
PWMSTA reflects the status of the PWM.
Table 37. PWMSTA MMR Bit Descriptions
Bit
Name
Description
15:10
–
Reserved.
9
PWMSYNCINT
PWM Sync Interrupt Bit. Writing a 1 to
this bit clears this interrupt.
8
PWMTRIPINT
PWM Trip Interrupt Bit. Writing a 1 to
this bit clears this interrupt.
3
PWMTRIP
Raw Signal from the PWMTRIP Pin.
2:1
Reserved.
0
PWMPHASE
PWM Phase Bit. Set to 1 by the Micro-
Converter when the timer is counting
down (1st half). Cleared to 0 by the
MicroConverter when the timer is
counting up (2nd half).
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