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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 19 of 92
Pin No.
7019/7020
7021
7022
Mnemonic
Description
11
10
P0.6/T1/MRST/PLAO[3]
Multifunction Pin. Driven low after reset. General-Purpose Output Port 0.6/
Timer1 Input/Power-On Reset Output/Programmable Logic Array Output
Element 3.
12
11
TCK
Test Clock, JTAG Test Port Input. Debug and download access.
13
12
TDO
Test Data Out, JTAG Test Port Output. Debug and download access.
14
13
IOGND
Ground for GPIO. Typically connected to DGND.
15
14
IOVDD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
16
15
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 μF capacitor to DGND only.
17
16
DGND
Ground for Core Logic.
18
17
P0.3/TRST/ADCBUSY
General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/
ADCBUSY Signal Output.
19
18
RST
Reset Input, Active Low.
20
19
IRQ0/P0.4/PWMTRIP/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-
Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable
Logic Array Output Element 1.
21
20
IRQ1/P0.5/ADCBUSY/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-
Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable
Logic Array Output Element 2.
22
21
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/
Programmable Logic Array Output Element 5/Start Conversion Input Signal
for ADC.
23
22
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/
Output for External Clock Signal/Input to the Internal Clock Generator
Circuits/UART/ Programmable Logic Array Output Element 4.
24
23
XCLKO
Output from the Crystal Oscillator Inverter.
25
24
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits.
26
25
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART,
SPI/Programmable Logic Array Output Element 0.
27
26
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART,
SPI/Programmable Logic Array Input Element 6.
28
27
P1.5/SPM5/PLAI[5]/IRQ3
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART,
SPI/Programmable Logic Array Input Element 5/External Interrupt
Request 3, Active High.
29
28
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART,
SPI/Programmable Logic Array Input Element 4/External Interrupt
Request 2, Active High.
30
29
P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART,
I2C1/Programmable Logic Array Input Element 3.
31
30
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART,
I2C1/Programmable Logic Array Input Element 2.
32
31
P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART,
I2C0/Programmable Logic Array Input Element 1.
33
32
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/
Timer1 Input/ UART, I2C0/Programmable Logic Array Input Element 0.
34
P4.2/PLAO[10]
General-Purpose Input and Output Port 4.2/Programmable Logic Array
Output Element 10.
35
34
33
VREF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor
when using the internal reference.
36
35
34
AGND
Analog Ground. Ground reference point for the analog circuitry.
37
36
35
AVDD
3.3 V Analog Power.
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