參數(shù)資料
型號： ADUC7021BCPZ62-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 10/92頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 1MSPS UART 40-LFCSP
標準包裝： 750
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 18 of 92
04
95
5-
0
66
ADuC7022
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
ADC5
ADC6
ADC7
ADC8
ADC9
GNDREF
TMS
TDI
BM/P0.0/CMPOUT/PLAI[7]
P0.6/T1/MRST/PLAO[3]
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
XCLKI
XCLKO
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P2.0/SPM9/PLAO[5]/CONVSTART
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
TC
K
TDO
IOGN
D
IOV
DD
LV
DD
DG
ND
P
0.
3/
T
RS
T
/ADC
BUSY
RS
T
IR
Q
0/P
0.4
/P
W
M
TR
IP
/P
L
A
O[
1]
IR
Q1
/P
0.
5/
A
D
C
BUSY
/P
L
A
O[
2]
A
DC4
A
DC3
/CM
P
1
A
DC2
/CM
P
0
A
DC1
A
DC0
AV
DD
AG
ND
V
REF
P
1.
0/
T
1/
SPM
0/
PL
A
I[
0]
P
1.
1/
SPM
1/
PL
AI
[1
]
40
39
38
37
36
35
34
33
32
31
Figure 12. 40-Lead LFCSP_VQ Pin Configuration (ADuC7022)
Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022)
Pin No.
7019/7020
7021
7022
Mnemonic
Description
38
37
36
ADC0
Single-Ended or Differential Analog Input 0.
39
38
37
ADC1
Single-Ended or Differential Analog Input 1.
40
39
38
ADC2/CMP0
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
1
40
39
ADC3/CMP1
Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/
Comparator Negative Input.
2
1
40
ADC4
Single-Ended or Differential Analog Input 4.
2
1
ADC5
Single-Ended or Differential Analog Input 5.
3
2
ADC6
Single-Ended or Differential Analog Input 6.
4
3
ADC7
Single-Ended or Differential Analog Input 7.
4
ADC8
Single-Ended or Differential Analog Input 8.
5
ADC9
Single-Ended or Differential Analog Input 9.
3
5
6
GNDREF
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from IOGND and DGND.
4
6
DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12.
5
7
DAC1/ADC13
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13.
6
DAC2/ADC14
DAC2 Voltage Output/Single-Ended or Differential Analog Input 14.
7
DAC3/ADC15
DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor
needs to be connected between this pin and AGND/Single-Ended or
Differential Analog Input 15.
8
7
TMS
Test Mode Select, JTAG Test Port Input. Debug and download access.
9
8
TDI
Test Data In, JTAG Test Port Input. Debug and download access.
10
9
BM/P0.0/CMPOUT/PLAI[7]
Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter
serial download mode if BM is low at reset and execute code if BM is
pulled high at reset through a 1 k
resistor/General-Purpose Input and
Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7.
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