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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 79/92頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 80 of 92
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated
by the 8-bit linear feedback shift register (LFSR) polynomial =
X8 + X6 + X5 + X + 1 as shown in Figure 68.
0
495
5-
0
38
CLOCK
QD
4
QD
5
QD
3
QD
7
QD
6
QD
2
QD
1
QD
0
Figure 68. 8-Bit LFSR
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload happens.
If it fails to match the expected state, a reset is immediately
generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always
guaranteed to force an immediate reset. The value of the LFSR
cannot be read; it must be tracked/generated in software.
Example of a sequence:
1.
Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
2.
Enter 0xAA in T3CLRI; Timer3 is reloaded.
3.
Enter 0x37 in T3CLRI; Timer3 is reloaded.
4.
Enter 0x6E in T3CLRI; Timer3 is reloaded.
5.
Enter 0x66. 0xDC was expected; the watchdog resets the chip.
EXTERNAL MEMORY INTERFACING
The ADuC7026 and ADuC7027 are the only models in their
series that feature an external memory interface. The external
memory interface requires a larger number of pins. This is why
it is only available on larger pin count packages. The XMCFG
MMR must be set to 1 to use the external port.
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
The memory interface can address up to four 128 kB of
asynchronous memory (SRAM or/and EEPROM).
The pins required for interfacing to an external memory are
shown in Table 79.
Table 79. External Memory Interfacing Pins
Pin
Function
AD[15:0]
Address/Data Bus.
A16
Extended Addressing for 8-Bit Memory Only.
MS[3:0]
Memory Select.
WS
Write Strobe.
RS
Read Strobe.
AE
Address Latch Enable.
BHE, BLE
Byte Write Capability.
There are four external memory regions available as described
in Table 80. Associated with each region are the MS[3:0] pins.
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 k × 8. To access 128 k with an 8-bit
memory, an extra address line (A16) is provided. (See the example
in Figure 69). The four regions are configured independently.
Table 80. Memory Regions
Address Start
Address End
Contents
0x10000000
0x1000FFFF
External Memory 0
0x20000000
0x2000FFFF
External Memory 1
0x30000000
0x3000FFFF
External Memory 2
0x40000000
0x4000FFFF
External Memory 3
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
0
49
55
-03
9
LATCH
ADuC7026/
ADuC7027
AD15:AD0
A16
EEPROM
64k × 16-BIT
A0:A15
D0:D15
CS
RAM
128k × 8-BIT
A0:A15
A16
D0:D7
CS
WE
OE
WE
OE
AE
MS0
MS1
WS
RS
Figure 69. Interfacing to External EEPROM/RAM
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