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| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 64/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 67 of 92
Table 59. SPISTA MMR Bit Descriptions
Bit
Description
7:6
Reserved.
5
SPIRX Data Register Overflow Status Bit. Set if SPIRX is
overflowing. Cleared by reading SPIRX register.
4
SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
3
SPIRX Data Register Full Status Bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
2
SPITX Data Register Underflow Status Bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
1
SPITX Data Register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
0
SPITX Data Register Empty Status Bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
SPIRX Register
Name
Address
Default Value
Access
SPIRX
0xFFFF0A04
0x00
R
SPIRX is an 8-bit read-only receive register.
SPITX Register
Name
Address
Default Value
Access
SPITX
0xFFFF0A08
0x00
W
SPITX is an 8-bit write-only transmit register.
SPIDIV Register
Name
Address
Default Value
Access
SPIDIV
0xFFFF0A0C
0x1B
R/W
SPIDIV is an 8-bit serial clock divider register.
SPICON Register
Name
Address
Default Value
Access
SPICON
0xFFFF0A10
0x0000
R/W
SPICON is a 16-bit control register.
Table 60. SPICON MMR Bit Descriptions
Bit
Description
Function
15:13
Reserved.
–
12
Continuous Transfer
Enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial
transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a
single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a
stall period.
11
Loop Back Enable.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
10
Slave Output Enable.
Set by user to enable the slave output enable. Cleared by user to disable slave output enable.
9
Slave Select Input Enable.
Set by user in master mode to enable the output. Cleared by user to disable master output.
8
SPIRX Overflow
Overwrite Enable.
Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by
user, the new serial byte received is discarded.
7
SPITX Underflow Mode.
Set by user to transmit 0. Cleared by user to transmit the previous data.
6
Transfer and Interrupt
Mode.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
5
LSB First Transfer
Enable Bit.
Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
4
Reserved.
–
3
Serial Clock Polarity
Mode Bit.
Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
2
Serial Clock Phase
Mode Bit.
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial
clock pulses at the end of each serial bit transfer.
1
Master Mode Enable Bit.
Set by user to enable master mode. Cleared by user to enable slave mode.
0
SPI Enable Bit.
Set by user to enable the SPI. Cleared by user to disable the SPI.
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