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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/92頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 51 of 92
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 30.
CMPCON Register
Name
Address
Default Value
Access
CMPCON
0xFFFF0444
0x0000
R/W
Table 30. CMPCON MMR Bit Descriptions
Bit
Value
Name
Description
15:11
Reserved.
10
CMPEN
Comparator Enable Bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
9:8
CMPIN
Comparator Negative Input
Select Bits.
00
AVDD/2.
01
ADC3 input.
10
DAC0 output.
11
Reserved.
7:6
CMPOC
Comparator Output Configuration
Bits.
00
Reserved.
01
Reserved.
10
Output on CMPOUT.
11
IRQ.
5
CMPOL
Comparator Output Logic State Bit.
When low, the comparator output
is high if the positive input (CMP0)
is above the negative input (CMP1).
When high, the comparator output
is high if the positive input is
below the negative input.
4:3
CMPRES
Response Time.
00
5 μs response time typical for large
signals (2.5 V differential).
17 μs response time typical for
small signals (0.65 mV differential).
11
3 μs typical.
01/10
Reserved.
2
CMPHYST
Comparator Hysteresis Bit. Set by
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
1
CMPORI
Comparator Output Rising Edge
Interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
0
CMPOFI
Comparator Output Falling Edge
Interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7019/20/21/22/24/25/26/27/28 integrates a 32.768 kHz
±
3% oscillator, a clock divider, and a PLL. The PLL locks onto a
multiple (1275) of the internal oscillator or an external 32.768 kHz
crystal to provide a stable 41.78 MHz clock (UCLK) for the system.
To allow power saving, the core can operate at this frequency, or
at binary submultiples of it. The actual core operating frequency,
UCLK/2CD, is refered to as HCLK. The default core clock is the
PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock
frequency can also come from an external clock on the ECLK
pin as described in Figure 56. The core clock can be outputted
on ECLK when using an internal oscillator or external crystal.
Note that when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
04955
-026
*32.768kHz ±3%
AT POWER UP
41.78MHz
OCLK
32.768kHz
WATCHDOG
TIMER
INT. 32kHz*
OSCILLATOR
CRYSTAL
OSCILLATOR
WAKEUP
TIMER
MDCLK
HCLK
PLL
CORE
I2C
UCLK
ANALOG
PERIPHERALS
/2CD
CD
XCLKO
XCLKI
P0.7/XCLK
P0.7/ECLK
Figure 56. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
External Crystal Selection
To switch to an external crystal, users must follow this procedure:
1.
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
2.
Follow the write sequence to the PLLCON register setting
the MDCLK bits to 01 and clearing the OSEL bit.
3.
Force the part into NAP mode by following the correct
write sequence to the POWCON register
4.
When the part is interrupted from NAP mode by the
Timer2 interrupt source, the clock source has switched to
the external clock.
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