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參數(shù)資料
| 型號： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 51/92頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標準包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 55 of 92
DESCRIPTION OF THE PWM BLOCK
A functional block diagram of the PWM controller is shown in
Figure 57. The generation of the six output PWM signals on
Pin PWM0H to Pin PWM2L is controlled by the following four
important blocks.
The 3-phase PWM timing unit. The core of the PWM
controller, this block generates three pairs of complemented
and dead-time-adjusted, center-based PWM signals. This
unit also generates the internal synchronization pulse,
PWMSYNC. It also controls whether the external PWMSYNC
pin is used or not.
The output control unit. This block can redirect the
outputs of the 3-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
The gate drive unit. This block can generate the high
frequency chopping and its subsequent mixing with the
PWM signals.
The PWM shutdown controller. This block takes care of
the PWM shutdown via the PWMTRIP pin and generates the
correct reset signal for the timing unit.
The PWM controller is driven by the ADuC7019/20/21/22/24/
25/26/27/28 core clock frequency and is capable of generating
two interrupts to the ARM core. One interrupt is generated on
the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
3-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit of
the PWM controller is
tCORE = 1/fCORE
where fCORE is the core frequency of the MicroConverter.
Therefore, for a 41.78 MHz fCORE, the fundamental time increment
is 24 ns. The value written to the PWMDAT0 register is effectively
the number of fCORE clock increments in a PWM period. The
required PWMDAT0 value is a function of the desired PWM
switching frequency (fPWN) and is given by
PWMDAT0 = fCORE/(2 × fPWM)
Therefore, the PWM switching period, tS, can be written as
tS = 2 × PWMDAT0 × tCORE
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0xFFFF = 65535, which corresponds to a minimum
PWM switching frequency of
fPWM(min) = 41.78 × 106/(2 × 65535) = 318.75 Hz
Note that a PWMDAT0 value of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the dead
time inserted into all three pairs of PWM output signals. The dead
time, tD, is related to the value in the PWMDAT1 register by:
tD = PWMDAT1 × 2 × tCORE
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can therefore be programmed in
increments of 2tCORE (or 49 ns for a 41.78 MHz core clock).
04
95
5-
027
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
PWMCON
PWMDAT0
PWMDAT1
PWMDAT2
PWMCH0
PWMCH1
PWMCH2
CONFIGURATION
REGISTERS DUTY CYCLE
REGISTERS
THREE-PHASE
PWM TIMING
UNIT
PWMEN
OUTPUT
CONTROL
UNIT
PWM
SHUTDOWN
CONTROLLER
PWMCFG
GATE
DRIVE
UNIT
PWMSYNC
PWMTRIP
TO INTERRUPT
CONTROLLER
SYNC
CORE CLOCK
Figure 57. Overview of the PWM Controller
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