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參數(shù)資料
| 型號(hào)： | ADUC7021BCPZ62-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 77/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲(chǔ)器容量： | 64KB（32K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28
Rev. B | Page 79 of 92
T2CLRI Register
Name
Address
Default Value
Access
T2CLRI
0xFFFF034C
0xFF
W
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
Timer3 (Watchdog Time)
Timer3 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 67).
04
95
5-
03
7
32.768kHz
PRESCALER
/1, 16 OR 256
16-BIT
UP/DOWN
COUNTER
16-BIT
LOAD
TIMER3
VALUE
WATCHDOG
RESET
TIMER3 IRQ
Figure 67. Timer3 Block Diagram
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register
until 0. T3LD is used as the timeout. The maximum timeout can
be 512 sec using the prescaler/256, and full-scale in T3LD.
Timer3 is clocked by the internal 32 kHz crystal when operating
in the watchdog mode. Note that to enter watchdog mode
successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name
Address
Default Value
Access
T3LD
0xFFFF0360
0x0000
R/W
T3LD is a 16-bit register load register.
T3VAL Register
Name
Address
Default Value
Access
T3VAL
0xFFFF0364
0xFFFF
R
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
T3CON Register
Name
Address
Default Value
Access
T3CON
0xFFFF0368
0x0000
R/W
T3CON is the configuration MMR described in Table 78.
Table 78. T3CON MMR Bit Descriptions
Bit
Value
Description
31:9
Reserved.
8
Count Up. Set by user for Timer3 to count up.
Cleared by user for Timer3 to count down by
default.
7
Timer3 Enable Bit. Set by user to enable Timer3.
Cleared by user to disable Timer3 by default.
6
Timer3 Mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
5
Watchdog Mode Enable Bit. Set by user to
enable watchdog mode. Cleared by user to
disable watchdog mode by default.
4
Secure Clear Bit. Set by user to use the secure
clear option. Cleared by user to disable the
secure clear option by default.
3:2
Prescale.
00
Source Clock/1 by Default.
01
Source Clock/16.
10
Source Clock/256.
11
Undefined. Equivalent to 00.
1
Watchdog IRQ Option Bit. Set by user to
produce an IRQ instead of a reset when
the watchdog reaches 0. Cleared by user to
disable the IRQ option.
0
Reserved.
T3CLRI Register
Name
Address
Default Value
Access
T3CLRI
0xFFFF036C
0x00
W
T3CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer3 interrupt in normal
mode or resets a new timeout period in watchdog mode.
Note that the user must perform successive writes to this
register to ensure resetting the timeout period.
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