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參數(shù)資料
| 型號： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 84/136頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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Operating in ALTEGO mode engages a second
improvement to the reception process. The
receiver checks for corruption of the preamble and
terminates reception of any frame which has
consecutive ’0’ bits. All valid preambles have an
alternating ’10’ pattern followed by the
Start-of-Frame delimiter (’11’). The above is
checked immediately on the assertion of the
internal carrier sense without any grace periods.
Neither of these causes for abort forces logic to set
RXE.
7.4.5
The Receiver computes the CRC of an incoming
frame serially. CRC computation includes address,
data, and CRC frame fields. It excludes preamble
and SFD. Computation stops after reception of last
whole octet following loss of carrier. The final value
of the CRC must be "C704DD7B" for the packet to
be validated.
CRC Checker
The CRC polynomial used is AUTODIN II:
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
+ X8 + X7 + X5 + X4 + X2 + X1 + 1.
If the received frame’s CRC does not check out, a
CRC error is indicated in the Status Register and
the CRC Error Counter is incremented. Frame
reception
will
terminate
Receive-with-Errors mode is enabled. In addition,
if the number of bits received in the last octet (when
the carrier is terminated) is greater than one and
less than 8 (a full octet), and the CRC check for all
complete octets fails, the frame is also labeled as
an ’alignment error’ and an error flag is set in the
Status Register; if this occurs, the Alignment Error
Counter will be incremented.
unless
the
7.4.6
Destination addresses that are ’individual’ are
compared to a 6-byte station address stored in
registers. If all bits match or if the PROMISCUOUS
mode is enabled, the frame is received.
Address Recognition Logic
A snapshot is taken of the partially-computed CRC
as the end of the destination field passes through
the CRC checker. If the address has the ’group’ or
’multicast’ bit set, 6 bits of this checksum are used
as a hashed index to a 64-bit Multicast Filter table.
If reception of multicast frames has been enabled
and if the 6-bit partial CRC points to a bit in the table
that has been turned on, the multicast frame will be
recognized. Broadcast frames are received when
the Broadcast Enable bit (RCON.BROAD) is active
or when the hashed bit in the Multicast Filter table
has been set.
To cause promiscuous reception of multicast and
broadcast frames, the entire Group Address table
should be turned on and reception of multicast
frames enabled.
If the address is rejected, the frame is also rejected
and none of the frame is transported to the buffer
memory. If the address is recognized, buffering of
the frame begins.
7.4.7
Received Byte Counter and Early
Receive Warning Interrupt
This circuit counts the number of bytes in each
completed frame and filters out runt frames (less
than 64 bytes) unless the runt filter is defeated by
setting the Accept Runt bit in the Receive
Configuration Register (RCON.RUNTS).
The Early Receive Warning (ERW) interrupt is
generated when the received byte count equals or
exceeds a value specified in the Early Receive
Warning Count Register (ERWCNT). The value of
ERWCNT is left-shifted four bits (multiplied by 16)
before it is compared to the receive byte count. The
value is 8 bits wide, allowing the ERW threshold to
be set between 0 and 4K with a resolution of 16
bytes.
The ERW interrupt is only generated if an active
reception is in progress. Once an early receive
interrupt has been set, it may be cleared and will
not be set again until another packet exceeds the
ERW threshold or the ERWCNT Register is written
to. Writing a value to ERWCNT that is less than the
current receive byte count (while reception is in
progress) will automatically set the ERW interrupt.
The ERW interrupt is mapped to bit 6 in the Interrupt
Status Register (INSTAT). The ERW interrupt is
enabled or disabled like all other interrupts by the
corresponding bit in the Interrupt Mask Register
(INTMASK).
LAN CONTROLLER OVERVIEW
83C795
71
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