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| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 52/136頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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Bit 6: CDH
, Collision Detect Heartbeat
This bit is set to a ’1’ during transmission of each
packet. It is set to ’0’ if a collision is detected within
3.6
μ
sec of the end of each packet transmission. If
no collision is detected within this window, it re-
mains ’1’.
Bit 5: UNDERFIFO
, FIFO or Buffer Underrun
When this bit is set, it means either:
a FIFO underrun condition has occurred. This
condition results when the transmit unit at-
tempts to read from an empty FIFO prior to
receiving the transmit done flag from DMA. This
means that the FIFO failed to supply enough
data for the serializer to maintain frame genera-
tion.
a Buffer underrun has occurred. This condition
happens when the transmit DMA accesses an
address that is greater than or equal to the most
recent host-written location in memory, pro-
vided that the Early Transmit Check feature is
enabled.
Bit 4: CRL
, Carrier Sense Lost
This bit is set if the carrier is lost during packet
transmission. Carrier sense is monitored from its
rising edge at the start of the outgoing frame’s echo.
Transmission is not aborted upon loss of carrier. It
is reported for statistical purposes.
Bit 3: ABORT
, Abort Transmission
This bit is set if the transmission is aborted due to
excessive collisions.
Bit 2: TWC
, Transmitted With Collisions
This bit is set if the frame collided at least once with
another frame on the network. It is not set for either
out-of-window collisions or excessive collision
aborts.
Bit 1: NDT
, Non-deferred Transmission
This bit is set if the frame was transmitted success-
fully without deferring. A deferred transmission can
only occur the first time an attempt is made to send
a packet. Collisions are not deferred transmissions.
Bit 0: PTX
, Packet Transmitted
This bit is set to indicate transmission of a packet
without excessive collisions or a FIFO underrun.
5.2.46 TTABH - Transmit Buffer Pointer High
Register
Linked-List Map Read/Write Port = 0:1B
This register contains the higher 8 bits of the
register pair used as a pointer to the transmit buffer
descriptors table. These registers should be
initialized to the same value as TBEGIN when the
descriptor table is created, and not altered
thereafter by the user unless the transmit buffer
pool is rebuilt. For more information, refer to page
80.
BIT
7
6
5
4
3
2
1
0
TTABH
RESET
X
X
X
X
X
X
X
X
A15
A14
A13
A12
A11
A10
A09
A08
5.2.47 TTABL - Transmit Buffer Pointer Low
Register
Linked-List Map Read/Write Port = 0:1A
This register contains the lower 8 bits of the register
pair used as a pointer to the transmit buffer
descriptor table. These registers should be
initialized to the same value as TBEGIN when the
descriptor table is created, and not altered
thereafter by the user unless the transmit buffer
pool is rebuilt.
BIT
7
6
5
4
3
2
1
0
TTABL
RESET
X
X
X
X
X
X
X
X
A07
A06
A05
A04
A03
A02
A01
A00
ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
39
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