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參數(shù)資料
| 型號： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 64/136頁 |
| 文件大小： | 1996K |
| 代理商： | 83C795 |
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6.5
MEMORY BUS STRUCTURE AND
CONFIGURATION
6.5.1
Because of the 83C795’s memory cache, the width
of the memory path is fixed at 8 bit. By means of
the memory cache, the I/O pipe can service either
an 8-bit or 16-bit host access. The Host and host
interface logic are programmed for a specific
memory width by setting bit 7 in the BIOS Page
Register, M16EN. (See page 17 for more on this
bit.)
Memory Bus Width Control
The 83C795 calculates the width of the host bus by
observing the MEMR line for transitions. An internal
flag (EEROM.HOST16) is set to indicate a 16-bit
host bus after 2 rising edges are seen on this pin.
When connected to an 8-bit host, this pin is left
unconnected or is tied to VDD and should not have
any transitions.
6.5.2
The BPR.M16EN bit in the BIOS Page Register
tells the host interface logic whether to make the
LAN adapter respond as a 16-bit or an 8-bit
peripheral to the host. The 83C795 responds to
either host bus width.
16-Bit Response To Host Access
When the host accesses memory, an address
comparator within the 83C795 looks at the
LA23-LA17 lines to determine if the 83C795’s
memory territory is being accessed. If it is and if
MPR.M16EN is set, the M16CS line is activated to
tell the host to run a 16-bit transfer cycle. When this
decision is based only on the LA address lines, it is
possible that the M16CS will be sent out when the
host is accessing a device other than 83C795 within
the same address range.
To allow finer resolution for the M16CS decode,
there is an optional means of including the decoding
of SA16-SA13 lines in the generation of the M16CS
response. This can be enabled by the FINE16 bit
of the Memory Page Register. Because the SA lines
are not guaranteed stable as early as LA lines, this
form of decoding can lead to erroneous results.
Be careful when you use this method. To avoid bus
width conflicts between buffer memory and the
ROM as well as conflicts with other cards in the
system, the 16-bit response should be turned on by
software only when that software can guarantee
that no access to the ROM is taking place and that
the only accesses within the 128K memory range
are to 16-bit devices. This may mean ensuring that
no access to any other card can take place. In
existing drivers, this is done by performing all 16-bit
transfers within interrupt service routines that keep
all other interrupts disabled during the transfer.
Take special care when writing IPL ROM code. If
the code actually gets executed out of ROM, the
ROM can potentially be configured within the same
128K block. The best advice is to copy code from
ROM to system memory outside the block or to
write code that does not enable 16-bit transfers.
The Host is provided with the ZWS signal in
accordance with whether the memory cache can
accommodate the transfer. The timing of this signal
is dependent upon the width of the transfer being
performed with the host.
To meet the memory bandwidth required by the ISA
bus, it is necessary to implement the buffer memory
HOST INTERFACE SECTION
83C795
51
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