參數(shù)資料
型號： 83C795
廠商： SMSC Corporation
英文描述： Ethernet System Controller
中文描述： 以太網(wǎng)系統(tǒng)控制器
文件頁數(shù)： 63/136頁
文件大?。?/td> 1996K
代理商： 83C795
6.3.2
The I/O address decoder compares the system
address lines SA15-SA13 and SA8-SA5 against a
programmable value. SA9 is compared to ’1’. The
lower group of lines gives a window size of 32 bytes
located on 32-byte boundaries over the range of
200H to 3E0H. The comparison with upper address
bits allows the window to be located outside the
base I/O area in the event there are multiple LAN
cards on the same backplane. This comparison is
qualified by the IOR, IOW, and the inverse of the
AEN lines. I/O base location possibilities are:
I/O Address Decode
0200, 0220, 0240, ..., 03E0
2200, 2220, 2240, ..., 23E0
4200, 4220, 4240, ..., 43E0
...
E200, E220, E240, ..., E3E0
Note
Only the first base location option is
supported by Plug and Play.
The I/O address is further decoded to resolve
between the LAN controller and registers
associated with the host interface based on the A4
address line.
6.3.2.1
This feature allows the I/O address decoding to be
changed to support the NEC PC-98 bus. This is
done by installing J UMPER7, which connects an
external resistor between MA7 and ground. When
enabled, the SA9-SA1 lines replace the SA8-SA0
lines, the SA12-SA10 lines must be all 1’s, and the
SA0 line must be zero for an I/O access to occur.
This remapping only affects I/O accesses and
leaves memory decoding unchanged.
PC-98 Bus Support
6.4
Two signals control much of the bus activity. They
are I/O Channel Ready (IORDY) and Zero Wait
State (ZWS). Each is explained below.
BUS CONTROL SIGNALS
6.4.1
The IORDY output is a high current, tri-state driver
which is normally turned off between accesses to
the board. It will actively drive low to indicate that
the board is not IORDY and drives high when
making the transition from ’not ready’ to ’ready’.
IORDY
Access to the internal registers of the LAN
controller is arbitrated by the LAN controller. This
arbitration is transparent to the host.
When host access is completed, IORDY is tri-stated
by the ending of the host’s strobes.
6.4.2
The Zero Wait State (ZWS) signal tells the
microprocessor that it can complete the present
bus cycle without inserting any additional wait
cycles. The response algorithm for the ZWS line
depends on the memory width, the host access
type, and whether the board has been enabled to
act as a 16-bit device. The appropriate type of ZWS
response logic is selected on the basis of memory
width and the M16EN control bit state.
Zero Wait State Response To Host
There is a Zero Wait Enable bit in one of the host
interface registers (CR.ZWSEN) which can be used
to prevent the 83C795 from asserting the Zero Wait
State signal.
83C795
HOST INTERFACE SECTION
50
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