參數(shù)資料
型號： 83C795
廠商： SMSC Corporation
英文描述： Ethernet System Controller
中文描述： 以太網(wǎng)系統(tǒng)控制器
文件頁數(shù)： 80/136頁
文件大?。?/td> 1996K
代理商： 83C795
7.1.3
This portion of the 83C795 is used to resolve
conflicts that can occur on data buses used by both
the DMA controller and host accesses to the
internal registers of the LAN Controller section.
LAN Controller Internal Bus Arbitration
The LAN bus arbitration section observes a LAN
select (CS) signal derived from the memory bus
arbiter and provides a ’ready’ handshake signal in
return. It also controls internal data flow within the
LAN controller and holds off the DMA
microcontroller during I/O accesses.
7.1.4
The core of the DMA controller is a ROM-based
microcontroller which includes an address counter
for the memory position, comparators for internal
address comparisons, some decrementers for loop
control, registers for storage of operating variables,
and I/O control signals that attach to many circuits
within the LAN controller section of the chip.
DMA Microcontroller
In addition to the microcode associated with normal
transmit, receive and loopback processes, there is
additional code to facilitate testing of the LAN
controller.
7.1.5
A request for LAN register access is made when the
host presents an I/O address that decodes to a
register within the upper 16 bytes of the 83C795’s
I/O block and a valid IOR or IOW is presented.
How to Access Registers
The chip will respond with an I/O Channel Not
Ready signal (IORDY) while internal arbitration
proceeds. It remains NOT IORDY until the desired
transfer is ready to be completed.
Access to the registers of the LAN controller section
is allowed after any ongoing DMA burst is
completed. At that time, the DMA may wish to
become active again in response to new needs, but
the arbitration logic will allow host access to the chip
until the I/O strobe becomes false. The arbiter
generates the IORDY signal as an indication to the
host that the internal bus has been made available
and that the requested I/O access has been made.
Between accesses to the chip, IORDY is undriven.
To read from a register, an I/O address is placed on
the SAxx pins and IOR is asserted by the host (must
be asserted after a valid address) and recognized
by the bus arbitration logic which enables data flow
from the addressed register to the D00-D07 pins.
Register reads are always done through the
D00-D07 pins, except for 16-bit I/O pipe accesses.
The D08-D15 pins will be tri-stated during read
operations. IORDY will indicate when the host may
sample data and terminate the read operation.
To write to a register, an I/O address is placed on
the SAxx pins and IOW is asserted by the host and
recognized by the bus arbiter. Address must
become stable before IOW is asserted. When the
bus is free for the transfer, IORDY is asserted. Data
is latched into an intermediate transfer latch with
the trailing edge of IOW and then transferred to the
destination register two clocks later.
This delayed write operation requires an internal
recovery period between host accesses to
registers. This period is documented in the detailed
timing diagrams.
7.1.6
The internal DMA controller moves packets
between buffer memory and the FIFOs.
Memory Interface
LAN CONTROLLER OVERVIEW
83C795
67
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