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| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁(yè)數(shù)： | 31/136頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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5.1.8
REV/IOPA - Revision/I/O Pipe Address
Register
Read/Write Port = 07
This register serves two functions:
1. It provides the host with revision information
about the chip (CHIP3-0 and REV3-0).
2. It provides a port for loading the I/O pipe
address into the buffer counter. For more on
this, see Section 6.2.
The revision information is read-only and will be
returned on reads to this location when the IOPAV
bit (ICR.5) is zero. This information is detailed as
follows:
BIT
7
6
5
4
3
2
1
0
REV READ
RESET
0
1
0
0
0
0
0
0
CHIP3
CHIP2
CHIP1
CHIP0
REV3
REV2
REV1
REV0
Bits 7-4: CHIP3-CHIP0
, Chip Type
Depending on the condition of J umper 9, this field
yields either 0100 or 0010. A value of 0100 indi-
cates to the host that this is an 83C795 device; a
value of 0010 indicates an 83C790 device.
Bits 3-0: REV3-REV0
, Revision Number
These bits initialize to the revision number of this chip.
When the I/O pipe is enabled – that is, when IOPEN
is set (ICR.4) – the I/O pipe address is loaded into
the buffer counter through this register. Since the
buffer counter is 16-bits wide, two consecutive
writes are required to accomplish this using this
method.
The first write, which contains the lower byte of
the address, is stored in a temporary register.
The second write, which contains the upper
byte of the address, is then transferred, along
with the contents of the temporary register, into
the buffer counter.
Any host access to the chip between the first and
second writes will automatically reset the process.
When IOPAV is set, the contents of the temporary
register can be read from this location.
BIT
7
6
5
4
3
2
1
0
IOPA
RESET
0
0
1
0
0
0
1
0
IOPA7
IOPA6
IOPA5
IOPA4
IOPA3
IOPA2
IOPA1
IOPA0
Bits 7-0: IOPA7-IOPA0
, I/O Pipe Address
This register provides the location of the I/O Pipe
address.
5.1.9
Read/Write Ports = 08 - 0D SWH = 0
LAN0 - LAN5 - LAN Address Registers
These six LAN address registers (along with the
BDID and CHKSUM registers) recall or store
general-purpose data from the EEROM and, during
normal use, recall the permanently-assigned LAN
address for the adapter.
REG
LAN0
LAN1
LAN2
LAN3
LAN4
LAN5
LN
RESET
0
0
0
0
0
0
INIT
EE
EE
EE
EE
EE
EE
RECALL
EE
EE
EE
EE
EE
EE
LN07-LN00
LN15-LN08
LN23-LN16
LN31-LN24
LN39-LN32
LNMSB,
LN46-LN40
Bits 0-7: LN07-LN00
In normal use, these are the least significant bits of
the globally-assigned LAN address block.
Bits 8-15: LN08-LN15
In normal use, LN8-LN15 are part of the globally
assigned LAN address block.
Bits 16-23: LN16-LN23
In normal use, LN16-LN23 are part of the globally
assigned LAN address block.
83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
18
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