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參數(shù)資料
| 型號(hào)： | 83C795 |
| 廠商： | SMSC Corporation |
| 英文描述： | Ethernet System Controller |
| 中文描述： | 以太網(wǎng)系統(tǒng)控制器 |
| 文件頁數(shù)： | 100/136頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | 83C795 |
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Figure 8-5 shows the same ring after proper
removal of the oldest received packet. The top ring,
FULLRING, shows a ring that is completely full. The
bottom ring, OVERFLOW, shows a ring on the
verge of overflow.
8.2.1.1
Automatic ring wrapping enables the host to read a
contiguous block of data from the buffer RAM
without having to check whether the block is so long
that the access wraps around the end of the buffer
ring. This is accomplished by checking whether the
next value to be loaded into the memory cache’s
buffer counter is equal to the register RSTOP. If this
is true, then the value of the RSTART register is
loaded into the counter instead. The memory
cache’s Host Counter is left unchanged so the host
can continue accessing memory past the end of the
ring, but instead receives the correct data from the
start of the ring. The comparison is only made when
the counter is incrementing so it is not possible to
Automatic Ring Wrapping
start the block of data past the ring’s end. Also,
since the host is sending addresses that are greater
than the end of the ring, it is required that the
83C795’s memory space extend beyond the end of
the ring. This can be accomplished by arranging the
memory space such that the transmit buffers come
after the receive buffer ring. This feature is enabled
by setting the WRAPEN bit (UBRCV.0). For more
on this, refer to page 40.
8.2.1.2
This is a read-only bit located at UBRCV.2 which
indicates to the host that there are no completely
received frames in the buffer ring yet. The host
checks this bit after it finishes receiving a frame and
quickly determines whether there are more frames
to copy. This bit is set when BOUND equals CURR.
BOUND is updated after CURR.
Ring-Empty Bit
Since this bit is only cleared for completely received
frames, another method must be used to determine
if there is a partial frame in the buffer that exceeds
FIGURE 8-5. RECEIVER BUFFER RING 2
BUFFER STRUCTURING AND DATA MOVEMENT PROCESSES
83C795
87
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