參數(shù)資料
型號(hào)： 28F640J5
英文描述： Dual-Slot, PCMCIA Analog Power Controller
中文描述： 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù)，32和64兆比特
文件頁(yè)數(shù)： 7/53頁(yè)
文件大?。?/td> 306K
代理商： 28F640J5
E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
7
PRELIMINARY
Table 1. Lead Descriptions
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when the device
is in x8 mode. This address is latched during a x8 program cycle. Not used in
x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is high).
A
1
–A
22
INPUT
ADDRESS INPUTS:
Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
32-Mbit: A
0
–A
21
64-Mbit: A
0
–A
22
DQ
0
–DQ
7
INPUT/
OUTPUT
LOW-BYTE DATA BUS:
Inputs data during buffer writes and programming, and
inputs commands during Command User Interface (CUI) writes. Outputs array,
query, identifier, or status data in the appropriate read mode. Floated when the
chip is de-selected or the outputs are disabled. Outputs DQ
6
–DQ
0
are also
floated when the Write State Machine (WSM) is busy. Check SR.7 (Status
Register bit 7) to determine WSM status.
DQ
8
–DQ
15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS:
Inputs data during x16 buffer writes and programming
operations. Outputs array, query, or identifier data in the appropriate read mode;
not used for Status Register reads. Floated when the chip is de-selected, the
outputs are disabled, or the WSM is busy.
CE
0
,
CE
1
,
CE
2
INPUT
CHIP ENABLES:
Activates the device’s control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 2,
Chip Enable
Truth Table
), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE
0
, CE
1
, or CE
2
that enables the device. Device
deselection occurs with the first edge of CE
0
, CE
1
, or CE
2
that disables the
device (see Table 2,
Chip Enable Truth Table
).
RP#
INPUT
RESET/ POWER-DOWN:
Resets internal automation and puts the device in
power-down mode. RP#-high enables normal operation. Exit from reset sets the
device to read array mode. When driven low, RP# inhibits write operations which
provides data protection during power transitions.
RP# at V
HH
enables master lock-bit setting and block lock-bits configuration
when the master lock-bit is set. RP# = V
HH
overrides block lock-bits thereby
enabling block erase and programming operations to locked memory blocks. Do
not permanently connect RP# to V
HH
.
OE#
INPUT
OUTPUT ENABLE:
Activates the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command User Interface, the Write
Buffer, and array blocks. WE# is active low. Addresses and data are latched on
the rising edge of the WE# pulse.
STS
OPEN
DRAIN
OUTPUT
STATUS:
Indicates the status of the internal state machine. When configured in
level mode (default mode), it acts as a RY/BY# pin. When configured in one of
its pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS pin, see the Configurations command.
Tie STS to V
CCQ
with a pull-up resistor.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640L18 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
28F640L30 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30)
28F640P3 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
28F640W30 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
28F650 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip
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