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| 型號(hào)： | 28F640J5 |
| 英文描述： | Dual-Slot, PCMCIA Analog Power Controller |
| 中文描述： | 28F640J5 -英特爾StrataFlash內(nèi)存技術(shù)，32和64兆比特 |
| 文件頁(yè)數(shù)： | 15/53頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | 28F640J5 |
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E
INTEL
StrataFlash MEMORY TECHNOLOGY, 32 AND 64 MBIT
15
PRELIMINARY
Table 3. Bus Operations
Mode
Notes
RP#
CE
0,1,2(10)
OE#
(11)
WE#
(11)
Address
V
PEN
DQ
(8)
STS
(default
mode)
Read Array
1,2,3
V
IH
or
V
HH
Enabled
V
IL
V
IH
X
X
D
OUT
High Z
(9)
Output
Disable
V
IH
or
V
HH
Enabled
V
IH
V
IH
X
X
High Z
X
Standby
V
IH
or
V
HH
Disabled
X
X
X
X
High Z
X
Reset/Power-
Down Mode
V
IL
X
X
X
X
X
High Z
High Z
(9)
Read
Identifier
Codes
V
IH
or
V
HH
Enabled
V
IL
V
IH
See
Figure 6
X
Note 4
High Z
(9)
Read Query
V
IH
or
V
HH
Enabled
V
IL
V
IH
See
Table 7
X
Note 5
High Z
(9)
Read Status
(WSM off)
V
IH
or
V
HH
Enabled
V
IL
V
IH
X
X
D
OUT
Read Status
(WSM on)
V
IH
or
V
HH
Enabled
V
IL
V
IH
X
V
PENH
DQ
7
= D
DQ
15
–8
= High Z
DQ
6–0
= High Z
Write
3,6,7
V
IH
or
V
HH
Enabled
V
IH
V
IL
X
X
D
IN
X
NOTES:
1.
2.
Refer to DC Characteristics When V
PEN
≤
V
PENLK
, memory contents can be read, but not altered.
X can be V
or V
IH
for control and address pins, and V
PENLK
or V
PENH
for V
PEN
. See DC Characteristicsfor V
PENLK
and
V
PENH
voltages.
In default mode, STS is V
when the WSM is executing internal block erase, program, or lock-bit configuration algorithms.
It is V
OH
when the WSM is not busy, in block erase suspend mode (with programming inactive), or reset/power-down
mode.
See Read Identifier Codes Commandsection for read identifier code data.
See Read Query Mode Commandsection for read query data.
Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
= V
and
V
is within specification. Block erase, program, or lock-bit configuration with V
IH
< RP# < V
HH
produce spurious results
and should not be attempted.
Refer to Table 4 for valid D
IN
during a write operation.
DQ refers to DQ
0
–DQ
7
if BYTE# is low and DQ
0
–DQ
15
if BYTE# is high.
High Z will be V
OH
with an external pull-up resistor.
10. See Table 2 for valid CE configurations.
11. OE# and WE# should never be enabled simultaneously.
3.
4.
5.
6.
7.
8.
9.
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